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CY23EP09SXI-1HT
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Infineon Cypress Semicon Clock Buffers, Drivers, Distributors, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CY23EP09SXI-1HT++**Infineon Cypress Semicon** · Clock Buffers, Drivers, Distributors · SOIC-16++CY23EP09SXI-1HT from Infineon Cypress Semicon, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | REF | input | Reference clock input, 10 MHz to 220 MHz maximum, weak pull-down |+| 2 | CLKA1 | tri_state | Bank A buffered clock output, tri-statable via S2:S1, weak pull-down |+| 3 | CLKA2 | tri_state | Bank A buffered clock output, tri-statable via S2:S1, weak pull-down |+| 4 | VDD | power_in | Supply voltage, 3.3 V or 2.5 V |+| 5 | GND | power_in | Ground |+| 6 | CLKB1 | tri_state | Bank B buffered clock output, tri-statable via S2:S1, weak pull-down |+| 7 | CLKB2 | tri_state | Bank B buffered clock output, tri-statable via S2:S1, weak pull-down |+| 8 | S2 | input | Select input bit 2, controls output configuration with S1, weak pull-ups |+| 9 | S1 | input | Select input bit 1, controls output configuration with S2, weak pull-ups |+| 10 | CLKB3 | tri_state | Bank B buffered clock output, tri-statable via S2:S1, weak pull-down |+| 11 | CLKB4 | tri_state | Bank B buffered clock output, tri-statable via S2:S1, weak pull-down |+| 12 | GND | power_in | Ground |+| 13 | VDD | power_in | Supply voltage, 3.3 V or 2.5 V |+| 14 | CLKA3 | tri_state | Bank A buffered clock output, tri-statable via S2:S1, weak pull-down |+| 15 | CLKA4 | tri_state | Bank A buffered clock output, tri-statable via S2:S1, weak pull-down |+| 16 | CLKOUT | output | Buffered output with internal 5 pF feedback load for PLL; external load adjusts zero delay, weak pull-down |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Infineon Cypress Semicon |+| Package | SOIC-16 |+| Category | Clock/Timing |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CY23EP09SXI-1HT`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cy23ep09sxi-1ht-etched.step` / `cy23ep09sxi-1ht-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cy23ep09sxi-1ht.step` / `cy23ep09sxi-1ht.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Infineon Cypress Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588904120178237440) (19 pp, sha256 `1dc3f01d2ee4c941`, retrieved 2026-09-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cy23ep09sxi-1ht-datasheet.pdf)
page.jsonadded+189@@ -0,0 +1,189 @@+{+ "slug": "cy23ep09sxi-1ht",+ "version": "0.1.0",+ "type": "component",+ "description": "Infineon Cypress Semicon Clock Buffers, Drivers, Distributors, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cy23ep09sxi-1ht",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cy23ep09sxi-1ht.kicad_sym",+ "cy23ep09sxi-1ht.kicad_mod",+ "cy23ep09sxi-1ht.glb",+ "cy23ep09sxi-1ht.step",+ "cy23ep09sxi-1ht.lbr",+ "docs/hero.png",+ "docs/cy23ep09sxi-1ht-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CY23EP09SXI-1HT",+ "manufacturer": "Infineon Cypress Semicon",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Clock/Timing",+ "subcategory": "Clock Buffers, Drivers, Distributors",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588904120178237440",+ "parts": {+ "symbol": "cy23ep09sxi-1ht.kicad_sym",+ "footprint": "cy23ep09sxi-1ht.kicad_mod",+ "model_3d": "cy23ep09sxi-1ht-etched.glb",+ "model_3d_plain": "cy23ep09sxi-1ht.glb",+ "model_3d_step": "cy23ep09sxi-1ht-etched.step",+ "model_3d_step_plain": "cy23ep09sxi-1ht.step",+ "lbr": "cy23ep09sxi-1ht.lbr"+ },+ "distributor_links": {+ "lcsc": "C2759943"+ },+ "pins": [+ {+ "number": "1",+ "name": "REF",+ "type": "input",+ "description": "Reference clock input, 10 MHz to 220 MHz maximum, weak pull-down"+ },+ {+ "number": "2",+ "name": "CLKA1",+ "type": "tri_state",+ "description": "Bank A buffered clock output, tri-statable via S2:S1, weak pull-down"+ },+ {+ "number": "3",+ "name": "CLKA2",+ "type": "tri_state",+ "description": "Bank A buffered clock output, tri-statable via S2:S1, weak pull-down"+ },+ {+ "number": "4",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage, 3.3 V or 2.5 V"+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Ground"+ },+ {+ "number": "6",+ "name": "CLKB1",+ "type": "tri_state",+ "description": "Bank B buffered clock output, tri-statable via S2:S1, weak pull-down"+ },+ {+ "number": "7",+ "name": "CLKB2",+ "type": "tri_state",+ "description": "Bank B buffered clock output, tri-statable via S2:S1, weak pull-down"+ },+ {+ "number": "8",+ "name": "S2",+ "type": "input",+ "description": "Select input bit 2, controls output configuration with S1, weak pull-ups"+ },+ {+ "number": "9",+ "name": "S1",+ "type": "input",+ "description": "Select input bit 1, controls output configuration with S2, weak pull-ups"+ },+ {+ "number": "10",+ "name": "CLKB3",+ "type": "tri_state",+ "description": "Bank B buffered clock output, tri-statable via S2:S1, weak pull-down"+ },+ {+ "number": "11",+ "name": "CLKB4",+ "type": "tri_state",+ "description": "Bank B buffered clock output, tri-statable via S2:S1, weak pull-down"+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground"+ },+ {+ "number": "13",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage, 3.3 V or 2.5 V"+ },+ {+ "number": "14",+ "name": "CLKA3",+ "type": "tri_state",+ "description": "Bank A buffered clock output, tri-statable via S2:S1, weak pull-down"+ },+ {+ "number": "15",+ "name": "CLKA4",+ "type": "tri_state",+ "description": "Bank A buffered clock output, tri-statable via S2:S1, weak pull-down"+ },+ {+ "number": "16",+ "name": "CLKOUT",+ "type": "output",+ "description": "Buffered output with internal 5 pF feedback load for PLL; external load adjusts zero delay, weak pull-down"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 19,+ "cost_usd": 0.2213,+ "at": "2026-09-21T15:38:20"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588904120178237440",+ "pages": 19,+ "sha256": "1dc3f01d2ee4c941",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}