CY2309SXC-1HT

@@ -0,0 +1,65 @@+# CY2309SXC-1HT++**Infineon Cypress Semicon** · Clock Buffers, Drivers, Distributors · SOIC-16++CY2309SXC-1HT from Infineon Cypress Semicon, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | REF | input | Input reference clock, 5-V tolerant input. Threshold voltage is VDD/2. Has a weak internal pull-down. |+| 2 | CLKA1 | output | Buffered clock output, Bank A. Weak pull-down on output. Drive strength: IOL=8 mA / IOH=-8 mA (-1) or 12 mA / -12 mA (-1H). |+| 3 | CLKA2 | output | Buffered clock output, Bank A. Weak pull-down on output. |+| 4 | VDD | power_in | 3.3 V supply. Operating range 3.0-3.6 V. Decouple with 0.1 µF close to pin. |+| 5 | GND | power_in | Ground reference for supply and I/O. |+| 6 | CLKB1 | output | Buffered clock output, Bank B. Weak pull-down on output. Bank B can be three-stated via S1/S2 select inputs. |+| 7 | CLKB2 | output | Buffered clock output, Bank B. Weak pull-down on output. |+| 8 | S2 | input | Select input, bit 2. With S1, decodes output source (PLL vs reference) and enables/three-states banks per Select Input Decoding table. Weak internal pull-up. |+| 9 | S1 | input | Select input, bit 1. Works with S2 to select PLL/reference output source and three-state Bank A/B. Weak internal pull-up. |+| 10 | CLKB3 | output | Buffered clock output, Bank B. Weak pull-down on output. |+| 11 | CLKB4 | output | Buffered clock output, Bank B. Weak pull-down on output. |+| 12 | GND | power_in | Ground reference for supply and I/O (second GND pin). |+| 13 | VDD | power_in | 3.3 V supply (second VDD pin). Operating range 3.0-3.6 V. Decouple with 0.1 µF close to pin. |+| 14 | CLKA3 | output | Buffered clock output, Bank A. Weak pull-down on output. |+| 15 | CLKA4 | output | Buffered clock output, Bank A. Weak pull-down on output. |+| 16 | CLKOUT | output | Buffered clock output that also provides the internal PLL feedback. Must be loaded to match the average CLKA/CLKB load to achieve zero input-to-output delay; loading imbalance adjusts skew per Figure 3. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Infineon Cypress Semicon |+| Package | SOIC-16 |+| Category | Clock/Timing |+| Pins | 16 |++## Ordering variants++Same part, different packaging or reel option.++- `CY2309SXC-1HT`+- `CY2309SXC-1HTSXCT`+- `CY2309SXC-1HTSXI`+- `CY2309SXC-1HTSXI-1H`+- `CY2309SXC-1HTZXC`+- `CY2309SXC-1HTZXC-1H`+- `CY2309SXC-1HTZXCT`+- `CY2309SXC-1HTZXI`+- `CY2309SXC-1HTZXI-1H`++## CAD (KiCad official)++- Symbol: `CY2309SXC-1HT`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Infineon Cypress Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588944330328956928) (25 pp, sha256 `2f8fa45e0635db50`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cy2309sxc-1ht-datasheet.pdf)

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