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Initial commit: component/cy2308sxi-2t

Ray ·855cae5441 ·
2 files changed +237
README.mdadded+51
@@ -0,0 +1,51 @@+# CY2308SXI-2T++**Infineon Cypress Semicon** · Clock Buffers, Drivers, Distributors · SOIC-16++CY2308SXI-2T from Infineon Cypress Semicon, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | REF | input | Input reference frequency with weak pull down |+| 2 | CLKA1 | output | Clock output, Bank A with weak pull down |+| 3 | CLKA2 | output | Clock output, Bank A with weak pull down |+| 4 | VDD | power_in | Power supply voltage, 3.0-3.6 V |+| 5 | GND | power_in | Power supply ground |+| 6 | CLKB1 | output | Clock output, Bank B with weak pull down |+| 7 | CLKB2 | output | Clock output, Bank B with weak pull down |+| 8 | S2 | input | Select input, bit 2 with weak pull up |+| 9 | S1 | input | Select input, bit 1 with weak pull up |+| 10 | CLKB3 | output | Clock output, Bank B with weak pull down |+| 11 | CLKB4 | output | Clock output, Bank B with weak pull down |+| 12 | GND | power_in | Power supply ground |+| 13 | VDD | power_in | Power supply voltage, 3.0-3.6 V |+| 14 | CLKA3 | output | Clock output, Bank A with weak pull down |+| 15 | CLKA4 | output | Clock output, Bank A with weak pull down |+| 16 | FBK | input | PLL feedback input |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Infineon Cypress Semicon |+| Package | SOIC-16 |+| Category | Clock/Timing |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CY2308SXI-2T`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Infineon Cypress Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588937292773249024) (21 pp, sha256 `4edc12b16d4a2d70`, retrieved 2026-09-17, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cy2308sxi-2t-datasheet.pdf)
page.jsonadded+186
@@ -0,0 +1,186 @@+{+  "slug": "cy2308sxi-2t",+  "version": "0.1.0",+  "type": "component",+  "description": "Infineon Cypress Semicon Clock Buffers, Drivers, Distributors, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "clock-timing",+    "cy2308sxi-2t",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cy2308sxi-2t.kicad_sym",+    "cy2308sxi-2t.kicad_mod",+    "cy2308sxi-2t.glb",+    "cy2308sxi-2t.step",+    "cy2308sxi-2t.lbr",+    "docs/hero.png",+    "docs/cy2308sxi-2t-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "CY2308SXI-2T",+    "manufacturer": "Infineon Cypress Semicon",+    "package": "SOIC-16",+    "pin_count": 16,+    "category": "Clock/Timing",+    "subcategory": "Clock Buffers, Drivers, Distributors",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588937292773249024",+    "parts": {+      "symbol": "cy2308sxi-2t.kicad_sym",+      "footprint": "cy2308sxi-2t.kicad_mod",+      "model_3d": "cy2308sxi-2t.glb",+      "model_3d_step": "cy2308sxi-2t.step",+      "lbr": "cy2308sxi-2t.lbr"+    },+    "distributor_links": {+      "lcsc": "C466881"+    },+    "pins": [+      {+        "number": "1",+        "name": "REF",+        "type": "input",+        "description": "Input reference frequency with weak pull down"+      },+      {+        "number": "2",+        "name": "CLKA1",+        "type": "output",+        "description": "Clock output, Bank A with weak pull down"+      },+      {+        "number": "3",+        "name": "CLKA2",+        "type": "output",+        "description": "Clock output, Bank A with weak pull down"+      },+      {+        "number": "4",+        "name": "VDD",+        "type": "power_in",+        "description": "Power supply voltage, 3.0-3.6 V"+      },+      {+        "number": "5",+        "name": "GND",+        "type": "power_in",+        "description": "Power supply ground"+      },+      {+        "number": "6",+        "name": "CLKB1",+        "type": "output",+        "description": "Clock output, Bank B with weak pull down"+      },+      {+        "number": "7",+        "name": "CLKB2",+        "type": "output",+        "description": "Clock output, Bank B with weak pull down"+      },+      {+        "number": "8",+        "name": "S2",+        "type": "input",+        "description": "Select input, bit 2 with weak pull up"+      },+      {+        "number": "9",+        "name": "S1",+        "type": "input",+        "description": "Select input, bit 1 with weak pull up"+      },+      {+        "number": "10",+        "name": "CLKB3",+        "type": "output",+        "description": "Clock output, Bank B with weak pull down"+      },+      {+        "number": "11",+        "name": "CLKB4",+        "type": "output",+        "description": "Clock output, Bank B with weak pull down"+      },+      {+        "number": "12",+        "name": "GND",+        "type": "power_in",+        "description": "Power supply ground"+      },+      {+        "number": "13",+        "name": "VDD",+        "type": "power_in",+        "description": "Power supply voltage, 3.0-3.6 V"+      },+      {+        "number": "14",+        "name": "CLKA3",+        "type": "output",+        "description": "Clock output, Bank A with weak pull down"+      },+      {+        "number": "15",+        "name": "CLKA4",+        "type": "output",+        "description": "Clock output, Bank A with weak pull down"+      },+      {+        "number": "16",+        "name": "FBK",+        "type": "input",+        "description": "PLL feedback input"+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 21,+        "cost_usd": 0.2195,+        "at": "2026-09-17T18:59:10"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588937292773249024",+        "pages": 21,+        "sha256": "4edc12b16d4a2d70",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file