cs8182ydfr8g

@@ -33,5 +33,79 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "CS8182YDFR8G",+    "manufacturer": "onsemi",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+    "datasheet": "https://www.onsemi.com/pdf/datasheet/cs8182ydfr8-d.pdf",+    "parts": {+      "symbol": "cs8182ydfr8g.kicad_sym",+      "footprint": "cs8182ydfr8g.kicad_mod",+      "model_3d": "cs8182ydfr8g-etched.glb",+      "model_3d_plain": "cs8182ydfr8g.glb",+      "model_3d_step": "cs8182ydfr8g-etched.step",+      "model_3d_step_plain": "cs8182ydfr8g.step",+      "lbr": "cs8182ydfr8g.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "VOUT",+        "type": "power_out",+        "description": "Regulated output. Sources up to 200 mA and tracks the VREF input (VOUT = VREF when Adj is tied to VOUT). Requires a ≥10 µF output capacitor for loop stability (ESR 0.1-1.0 Ω @ 10 kHz)."+      },+      {+        "number": "2",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return. Pins 2, 3, 6, 7 in the SO-8 package are all internally bonded to the ground / thermal lead frame (internally fused leads) and should all be tied to the PCB ground plane for thermal dissipation."+      },+      {+        "number": "3",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return. Internally fused with pins 2, 6, and 7 to serve as the SO-8 thermal path. Tie to the PCB ground/heatsink copper."+      },+      {+        "number": "4",+        "name": "Adj",+        "type": "input",+        "description": "Adjust lead - inverting input of the internal tracking op-amp. Tie directly to VOUT for VOUT = VREF, or drive from a resistor divider between VOUT and GND (or between VOUT and an external reference) to set VOUT above or below VREF. Draws only ~0.2 µA typ (1.0 µA max) bias current in regulation."+      },+      {+        "number": "5",+        "name": "VREF/ENABLE",+        "type": "input",+        "description": "Reference voltage and enable input - non-inverting input of the internal tracking op-amp. Applying a valid reference (>2.75 V typ) enables the regulator and sets the target VOUT. Pulling this pin below 0.80 V (typ 2.00 V threshold) puts the device into sleep mode drawing ~30 µA (55 µA max). Input bias 0.2 µA typ, 1.0 µA max."+      },+      {+        "number": "6",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return. Internally fused with pins 2, 3, and 7 to form the SO-8 thermal path. Tie to the PCB ground/heatsink copper."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return. Internally fused with pins 2, 3, and 6 to form the SO-8 thermal path. Tie to the PCB ground/heatsink copper."+      },+      {+        "number": "8",+        "name": "VIN",+        "type": "power_in",+        "description": "Unregulated input supply. Recommended continuous operating range 3.4 V to 45 V (absolute maximum −16 V to +45 V, tolerant of 45 V load-dump and −50 V reverse polarity transients). A 1.0 µF bypass capacitor (C1) is recommended if the regulator is remote from the power source filter."+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}