cs8182ydfr8g

@@ -0,0 +1,52 @@+# CS8182YDFR8G++**onsemi** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8++CS8182YDFR8G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VOUT | power_out | Regulated output. Sources up to 200 mA and tracks the VREF input (VOUT = VREF when Adj is tied to VOUT). Requires a ≥10 µF output capacitor for loop stability (ESR 0.1-1.0 Ω @ 10 kHz). |+| 2 | GND | power_in | Ground return. Pins 2, 3, 6, 7 in the SO-8 package are all internally bonded to the ground / thermal lead frame (internally fused leads) and should all be tied to the PCB ground plane for thermal dissipation. |+| 3 | GND | power_in | Ground return. Internally fused with pins 2, 6, and 7 to serve as the SO-8 thermal path. Tie to the PCB ground/heatsink copper. |+| 4 | Adj | input | Adjust lead - inverting input of the internal tracking op-amp. Tie directly to VOUT for VOUT = VREF, or drive from a resistor divider between VOUT and GND (or between VOUT and an external reference) to set VOUT above or below VREF. Draws only ~0.2 µA typ (1.0 µA max) bias current in regulation. |+| 5 | VREF/ENABLE | input | Reference voltage and enable input - non-inverting input of the internal tracking op-amp. Applying a valid reference (>2.75 V typ) enables the regulator and sets the target VOUT. Pulling this pin below 0.80 V (typ 2.00 V threshold) puts the device into sleep mode drawing ~30 µA (55 µA max). Input bias 0.2 µA typ, 1.0 µA max. |+| 6 | GND | power_in | Ground return. Internally fused with pins 2, 3, and 7 to form the SO-8 thermal path. Tie to the PCB ground/heatsink copper. |+| 7 | GND | power_in | Ground return. Internally fused with pins 2, 3, and 6 to form the SO-8 thermal path. Tie to the PCB ground/heatsink copper. |+| 8 | VIN | power_in | Unregulated input supply. Recommended continuous operating range 3.4 V to 45 V (absolute maximum −16 V to +45 V, tolerant of 45 V load-dump and −50 V reverse polarity transients). A 1.0 µF bypass capacitor (C1) is recommended if the regulator is remote from the power source filter. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | SOIC-8 |+| Category | PMIC |+| Pins | 8 |++## Ordering variants++- `CS8182YDFR8GYDF8G`+- `CS8182YDFR8G`+- `CS8182YDFR8GYDPS5G`+- `CS8182YDFR8GYDPSR5G`+- `CS8182YDFR8GDTG`+- `CS8182YDFR8GDTRKG`++## CAD (KiCad official)++- Symbol: `CS8182YDFR8G`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/cs8182ydfr8-d.pdf) (None pp, sha256 `748827199c8f4afc`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cs8182ydfr8g-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "cs8182ydfr8g",+  "version": "0.1.0",+  "type": "component",+  "description": "onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "pmic",+    "cs8182ydfr8g"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cs8182ydfr8g.kicad_sym",+    "cs8182ydfr8g.kicad_mod",+    "cs8182ydfr8g.glb",+    "cs8182ydfr8g.step",+    "cs8182ydfr8g.lbr",+    "docs/hero.png",+    "docs/cs8182ydfr8g-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file