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CS1238-SOP14
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CHIPSEA Analog To Digital Converters (ADC), SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# CS1238-SOP14++**CHIPSEA** · Analog To Digital Converters (ADC) · SOP-14++CS1238-SOP14 from CHIPSEA, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD | power_in | Power supply input. Operates from 3.0-3.6 V or 4.5-5.5 V; absolute max 6 V. Also serves as the analog and digital supply for the ADC core. |+| 2 | REFOUT | power_out | Internal reference voltage output (typ. = VDD). Also acts as the excitation source output for bridge/temperature sensors. |+| 3 | REFIN | input | Reference voltage input for the ADC. Accepts 1.5 V to VDD+0.1 V. When using an external reference, the internal reference must first be disabled via the refo_off register bit. |+| 4 | GND | power_in | Chip ground reference. Tie to system ground. |+| 5 | NC | unconnected | No connect. Leave floating or tie to ground. |+| 6 | AINP1 | input | Channel 1 positive differential analog input. Full-scale differential input is ±0.5·VREF/PGA. Common-mode range: AGND-0.1 to AVDD+0.1 (PGA=1/2), AGND+0.75 to AVDD-0.75 (PGA=64/128). |+| 7 | AINN1 | input | Channel 1 negative differential analog input. Paired with AINP1. |+| 8 | AINP2 | input | Channel 2 positive differential analog input. Selected via the ch_sel[1:0] register bits. |+| 9 | AINN2 | input | Channel 2 negative differential analog input. Paired with AINP2. |+| 10 | NC | unconnected | No connect. Leave floating or tie to ground. |+| 11 | GND | power_in | Chip ground reference (second GND pin). Tie to system ground. |+| 12 | NC | unconnected | No connect. Leave floating or tie to ground. |+| 13 | SCLK | input | Serial clock input from the MCU. Max frequency 1.1 MHz. Holding SCLK high for >100 µs puts the device into power-down mode; returning SCLK low resumes normal operation with prior register state preserved. |+| 14 | DRDY/DOUT | bidirectional | Muxed data-ready / serial data pin (active-low DRDY, DOUT for data + control). Goes low to signal new ADC data is available, then clocks out 24-bit conversion data and accepts configuration writes on SCLK edges. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | CHIPSEA |+| Package | SOP-14 |+| Category | Data Acquisition |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CS1238-SOP14`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [CHIPSEA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586176486470520832) (20 pp, sha256 `db86629558b82515`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cs1238-sop14-datasheet.pdf)
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