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Set visibility: public

Ray ·1e568dcd3b · ·parent 539a7f4
1 file changed +6−3
page.json+6−3
@@ -62,7 +62,7 @@         "number": "6",         "name": "AINP1",         "type": "input",-        "description": "Channel 1 positive differential analog input. Full-scale differential input is \u00b10.5\u00b7VREF/PGA. Common-mode range: AGND-0.1 to AVDD+0.1 (PGA=1/2), AGND+0.75 to AVDD-0.75 (PGA=64/128)."+        "description": "Channel 1 positive differential analog input. Full-scale differential input is ±0.5·VREF/PGA. Common-mode range: AGND-0.1 to AVDD+0.1 (PGA=1/2), AGND+0.75 to AVDD-0.75 (PGA=64/128)."       },       {         "number": "7",@@ -104,7 +104,7 @@         "number": "13",         "name": "SCLK",         "type": "input",-        "description": "Serial clock input from the MCU. Max frequency 1.1 MHz. Holding SCLK high for >100 \u00b5s puts the device into power-down mode; returning SCLK low resumes normal operation with prior register state preserved."+        "description": "Serial clock input from the MCU. Max frequency 1.1 MHz. Holding SCLK high for >100 µs puts the device into power-down mode; returning SCLK low resumes normal operation with prior register state preserved."       },       {         "number": "14",@@ -175,5 +175,8 @@     "docs/cs1238-sop14-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file