Codex

@@ -4,7 +4,7 @@   "type": "app",   "title": "Codex",   "brief": "Codex in Adom Hydrogen: ecosystem setup, dock dashboard and live engineering demos.",-  "version": "0.1.3",+  "version": "0.1.4",   "hero": {     "type": "image",     "path": "screenshots/hero.png"

@@ -0,0 +1,40 @@+---+name: codex-adom-ablation-routing+description: Route PCBs for copper ablation by retaining copper on every layer, including intentionally floating islands when requested. Measure native filled copper coverage, preserve electrical isolation, and record reproducible CAD demonstrations.+---+Parent skill: codex-adom++# PCB routing for copper ablation++For subtractive ablation, routing connectivity is only one objective. Starting from copper-clad material, maximize retained copper subject to electrical, geometric and manufacturing constraints. A trace-only layout with empty surrounding FR4 does not satisfy a request for minimum copper removal.++Establish the process's minimum isolation-channel width and manufacturing tolerance. Treat this as a fabrication limit, not a voltage-independent clearance rule. Preserve larger applicable clearances. Establish maximum differential working voltage, switching/transient peaks, environment, coating, altitude and insulation category before claiming electrical safety. Clearance through air and creepage along a surface are separate checks; consult current primary guidance and the applicable end-product standard. Never invent a universal voltage-to-gap threshold from nominal air breakdown strength.++Keep an isolated copy of the source and the trace-only routed checkpoint. Recheck the selected host, bridge pin, active document and actual editor identity before mutation. Use the current app bridge's supported native polygon/pour interface. In Fusion, a file-open call can fail on a path containing spaces; verify existence, then copy to a unique user-writable path without spaces and open that copy if needed. Never infer failure from a timeout without checking state.++## Copper strategy++- Use net-connected copper where it has an appropriate electrical function. Retain islands only when the user's ablation objective permits floating copper; do not apply this policy to unrelated board work.+- A polygon's nominal net name does not prove every filled contour is connected. Distinguish connected copper from physically floating orphan regions after refill.+- Floating copper is conductive material with an uncontrolled potential. Do not insert it into required isolation barriers or count it as insulating distance. Preserve appropriate keepouts around sensitive nodes and any required high-voltage separation.+- Fill each active copper layer within the board boundary, accounting for edge clearance, drills, keepouts, net clearances and local width limits. Do not change stackup or reduce an existing electrical clearance merely to increase coverage.+- In Fusion, solid polygons with `orphans=yes` retain otherwise discarded isolated regions. Thermal connections, solid connections, polygon rank and minimum neck width affect the fill and must be selected deliberately. Use native refill and inspect actual results.+- Maximal ground fill is one candidate, not proof of globally optimal copper use. Broader power copper and local net-assigned regions can improve electrical behavior; narrow pre-existing power routes are not qualified merely by filling ground around them.++## Verification and measurement++Force a native refill before export, connectivity checks or area measurement. Outlines and stale cached fill are not sufficient. Preserve the native exported filled geometry, DRC report, board hash, input rules and chosen process constraints.++Compute copper area from the union of filled polygons, tracks, pads and vias, clipped to the board outline; subtract polygon holes and actual drill voids. Avoid double-counting overlaps. Report each copper layer and the total projected area across layers. State the denominator and geometric approximations. Report the area-to-remove reduction relative to the same trace-only board, not just the increase in copper percentage. Area is not a measured machining-time reduction: scan strategy, channel passes, spot size and motion overhead also matter.++Compare fresh native DRC and connectivity with the baseline under the same rule profile. Preserve pre-existing error signatures and separately report new errors. Check copper islands, shorts, clearances and narrow residual gaps. Check voltage-specific requirements separately; native DRC proves only the rules actually encoded.++If an inherited rule is inconsistent with intended connectivity, diagnose it on comparison copies, disclose the exact change, and retain the unmodified reference. Never hide violations by suppressing rules to improve the video result.++## Reproducible video++Use codex-adom-routing-video for native recording and narration, and codex-adom-desktop-artifacts for host playback. Show the original reference, independent routing, trace-only checkpoint, layer-by-layer pours, isolation close-ups, floating islands, measured coverage and native validation. The objective should be stated at the opening: retain copper while preserving electrical separation.++Record genuine CAD changes and retain raw captures. Distinguish precomputed planning from live geometry creation, edited takes from continuous recording, and playback speed from elapsed computation time. Narrate the actual measured result, selected process limit, larger electrical clearances, and remaining engineering work.++For the BQ25792 example and its evolving acceptance evidence, read [references/bq25792.md](references/bq25792.md). Example dimensions and net names are not universal defaults.

@@ -0,0 +1,18 @@+# BQ25792 example++Source: public wiki project `adom/bq25792-charger`, Adonis's Fusion design. Routing implementation source: `adom/fusion-bridge`, branch `feature/per-net-trace-routing`, directory `demo/routing/bq25792/`. The original route demo and narrated version are committed separately from the later copper-retention work.++The trace-only native checkpoint has 109 components, 50 nets, 612 segments, 60 vias and zero pours on four layers (1, 2, 15, 16), with a 50.4 x 26.4 mm outline. Fresh native checks reported zero airwires, zero warnings and one pre-existing placement-clearance error. That is the baseline, not a full-pour result.++The user specified 0.1 mm process isolation and explicitly requested retaining floating copper to reduce ablation. Existing larger electrical clearances, including 0.2 mm edge clearance, remain constraints. TI specifies a 3.6–24 V input range for the BQ25792; this is not certification of a 0.1 mm channel for all net pairs or environmental conditions.++The comparison profile disables the source's all-object same-net spacing rule, which otherwise rejects intended same-net connections. All different-net rules remain enabled. The unmodified reference is preserved. The remaining baseline placement error signature is `5,1,f10227fd41e0ab5d`. Do not automatically copy this exception into another design.++Copper-retention results must be taken from the completed ablation evidence, not from these trace-only numbers. The native filled export is the authority for polygon area and orphan classification. Do not claim production power/thermal or insulation qualification from geometric connectivity alone.++Primary references:++- [TI BQ25792 evaluation-board specifications](https://www.ti.com/tool/BQ25792EVM)+- [TI clearance and creepage guidance](https://www.ti.com/lit/ml/slup421/slup421.pdf)+- [Fusion polygon parameters and orphan behavior](https://help.autodesk.com/cloudhelp/ENU/Fusion-ECAD/files/ECD-CLI-P.htm)+- [Fusion native polygon fill contours](https://help.autodesk.com/cloudhelp/ENU/Fusion-ECAD/files/ECD-ULP-POLYPOUR.htm)