CN825S

@@ -60,6 +60,18 @@   <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="5" x="1.1375" y="-0.0000" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="6" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-1.4500" y="1.5100"/>+    <vertex x="-1.6900" y="1.8400"/>+    <vertex x="-1.2100" y="1.8400"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.4000" y="1.4500"/>+    <vertex x="0.8000" y="1.4500"/>+    <vertex x="0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="1.0500"/>+  </polygon>   <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@   <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/>   <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="CN825S">@@ -102,7 +114,13 @@         <connect gate="G$1" pin="RESET" pad="5"/>         <connect gate="G$1" pin="VCC" pad="4"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="CN825S" constant="no"/>+          <attribute name="MANUFACTURER" value="ShangHai Consonance Elec" constant="no"/>+          <attribute name="LCSC_PN" value="C3034869" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>

@@ -26,13 +26,15 @@       "model_3d_step": "cn825s.step",       "lbr": "cn825s.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C3034869"+    },     "pins": [       {         "number": "1",         "name": "MR",         "type": "input",-        "description": "Active-low manual reset input. Pulling MR low triggers a reset pulse. Internally pulled up to VCC through a 50kΩ resistor (38-62kΩ), so the pin may be left floating, driven by CMOS logic, or driven by open-drain/open-collector output. Minimum pulse width 1µs; MR-to-reset delay 500ns typ."+        "description": "Active-low manual reset input. Pulling MR low triggers a reset pulse. Internally pulled up to VCC through a 50k\u03a9 resistor (38-62k\u03a9), so the pin may be left floating, driven by CMOS logic, or driven by open-drain/open-collector output. Minimum pulse width 1\u00b5s; MR-to-reset delay 500ns typ."       },       {         "number": "2",@@ -44,25 +46,25 @@         "number": "3",         "name": "/RESET",         "type": "output",-        "description": "Active-low reset output. Driven low when VCC falls below the reset threshold (2.93V typ for CN825S), when MR is low, or when the watchdog timer overflows. After the fault clears, /RESET remains low for at least 140ms (200ms typ) before returning high. Guaranteed valid down to VCC = 1.1V. VOL ≤ 0.3V @ ISINK=3.2mA; VOH ≥ VCC−1V @ ISOURCE=1mA."+        "description": "Active-low reset output. Driven low when VCC falls below the reset threshold (2.93V typ for CN825S), when MR is low, or when the watchdog timer overflows. After the fault clears, /RESET remains low for at least 140ms (200ms typ) before returning high. Guaranteed valid down to VCC = 1.1V. VOL \u2264 0.3V @ ISINK=3.2mA; VOH \u2265 VCC\u22121V @ ISOURCE=1mA."       },       {         "number": "4",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply input; also the monitored voltage compared against the internal reset threshold. Operating range 1.1V to 6.5V, absolute max 6.5V. Supply current ≈2.7µA below the reset threshold, ≈16µA above."+        "description": "Positive supply input; also the monitored voltage compared against the internal reset threshold. Operating range 1.1V to 6.5V, absolute max 6.5V. Supply current \u22482.7\u00b5A below the reset threshold, \u224816\u00b5A above."       },       {         "number": "5",         "name": "RESET",         "type": "output",-        "description": "Active-high reset output. Driven high when VCC is below the reset threshold, when MR is low, or when the watchdog overflows. After the fault clears, RESET remains high for at least 140ms (200ms typ) before returning low. VOH ≥ VCC−1V @ ISOURCE=1mA; VOL ≤ 0.3V @ ISINK=3.2mA."+        "description": "Active-high reset output. Driven high when VCC is below the reset threshold, when MR is low, or when the watchdog overflows. After the fault clears, RESET remains high for at least 140ms (200ms typ) before returning low. VOH \u2265 VCC\u22121V @ ISOURCE=1mA; VOL \u2264 0.3V @ ISINK=3.2mA."       },       {         "number": "6",         "name": "WDI",         "type": "input",-        "description": "Watchdog input. Must transition (high-to-low or low-to-high) at least once every 1.6s (typ; 0.95s min, 2.25s max) or the watchdog overflows and asserts both reset outputs for ≥140ms. Minimum edge pulse width 50ns. Input leakage ±50nA. Logic thresholds VIL ≤ 0.25*VCC, VIH ≥ 0.75*VCC."+        "description": "Watchdog input. Must transition (high-to-low or low-to-high) at least once every 1.6s (typ; 0.95s min, 2.25s max) or the watchdog overflows and asserts both reset outputs for \u2265140ms. Minimum edge pulse width 50ns. Input leakage \u00b150nA. Logic thresholds VIL \u2264 0.25*VCC, VIH \u2265 0.75*VCC."       }     ],     "provenance": {