← Commit history

Set visibility: public

Ray ·979e282b3e · ·parent b08d440
1 file changed +9−6
page.json+9−6
@@ -32,7 +32,7 @@         "number": "1",         "name": "/MR",         "type": "input",-        "description": "Active-low manual reset input. Pulling this pin low triggers a reset pulse on both reset outputs. Internally pulled up to VCC via a ~50 k\u03a9 resistor (38-62 k\u03a9), so it can be left floating, driven by CMOS, or driven by open-drain/open-collector logic. Minimum pulse width 1 \u00b5s; MR-to-reset delay \u2264500 ns."+        "description": "Active-low manual reset input. Pulling this pin low triggers a reset pulse on both reset outputs. Internally pulled up to VCC via a ~50 kΩ resistor (38-62 kΩ), so it can be left floating, driven by CMOS, or driven by open-drain/open-collector logic. Minimum pulse width 1 µs; MR-to-reset delay ≤500 ns."       },       {         "number": "2",@@ -44,25 +44,25 @@         "number": "3",         "name": "/RESET",         "type": "output",-        "description": "Active-low reset output. Driven low when VCC is below the 2.63 V reset threshold, when /MR is low, or when the watchdog times out. After the condition clears, /RESET stays low for at least 140 ms (typ. 200 ms) before returning high. VOL = 0.3 V max at 3.2 mA sink (150 \u00b5A at VCC = 1.1 V)."+        "description": "Active-low reset output. Driven low when VCC is below the 2.63 V reset threshold, when /MR is low, or when the watchdog times out. After the condition clears, /RESET stays low for at least 140 ms (typ. 200 ms) before returning high. VOL = 0.3 V max at 3.2 mA sink (150 µA at VCC = 1.1 V)."       },       {         "number": "4",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply input, 1.1 V to 6.5 V operating range. This pin is continuously monitored and compared to the internal 2.63 V (CN825R) reset threshold. Supply current 2.7 \u00b5A typ. below threshold, 16 \u00b5A typ. above threshold. Abs max 6.5 V, 20 mA."+        "description": "Positive supply input, 1.1 V to 6.5 V operating range. This pin is continuously monitored and compared to the internal 2.63 V (CN825R) reset threshold. Supply current 2.7 µA typ. below threshold, 16 µA typ. above threshold. Abs max 6.5 V, 20 mA."       },       {         "number": "5",         "name": "RESET",         "type": "output",-        "description": "Active-high reset output. Driven high when VCC is below the reset threshold, when /MR is low, or when the watchdog times out. After the condition clears, RESET stays high for at least 140 ms (typ. 200 ms) before returning low. VOH = VCC\u22121 V min at 1 mA source (1.0 V min at VCC = 1.1 V, 8 \u00b5A)."+        "description": "Active-high reset output. Driven high when VCC is below the reset threshold, when /MR is low, or when the watchdog times out. After the condition clears, RESET stays high for at least 140 ms (typ. 200 ms) before returning low. VOH = VCC−1 V min at 1 mA source (1.0 V min at VCC = 1.1 V, 8 µA)."       },       {         "number": "6",         "name": "WDI",         "type": "input",-        "description": "Watchdog input. If WDI is held high or low for more than the watchdog timeout (typ. 1.6 s, min 0.95 s, max 2.25 s) without a logic transition, the watchdog expires and asserts both reset outputs for \u2265140 ms. Input high threshold 0.75\u00b7VCC, low threshold 0.25\u00b7VCC; input current \u00b150 nA; minimum detectable pulse width 50 ns."+        "description": "Watchdog input. If WDI is held high or low for more than the watchdog timeout (typ. 1.6 s, min 0.95 s, max 2.25 s) without a logic transition, the watchdog expires and asserts both reset outputs for ≥140 ms. Input high threshold 0.75·VCC, low threshold 0.25·VCC; input current ±50 nA; minimum detectable pulse width 50 ns."       }     ],     "provenance": {@@ -126,5 +126,8 @@     "docs/cn825r-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file