CN825R

@@ -60,6 +60,18 @@   <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="5" x="1.1375" y="-0.0000" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="6" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-1.4500" y="1.5100"/>+    <vertex x="-1.6900" y="1.8400"/>+    <vertex x="-1.2100" y="1.8400"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.4000" y="1.4500"/>+    <vertex x="0.8000" y="1.4500"/>+    <vertex x="0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="1.0500"/>+  </polygon>   <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@   <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/>   <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="CN825R">@@ -102,7 +114,13 @@         <connect gate="G$1" pin="RESET" pad="5"/>         <connect gate="G$1" pin="VCC" pad="4"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="CN825R" constant="no"/>+          <attribute name="MANUFACTURER" value="ShangHai Consonance Elec" constant="no"/>+          <attribute name="LCSC_PN" value="C3034868" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>

@@ -26,13 +26,15 @@       "model_3d_step": "cn825r.step",       "lbr": "cn825r.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C3034868"+    },     "pins": [       {         "number": "1",         "name": "/MR",         "type": "input",-        "description": "Active-low manual reset input. Pulling this pin low triggers a reset pulse on both reset outputs. Internally pulled up to VCC via a ~50 kΩ resistor (38-62 kΩ), so it can be left floating, driven by CMOS, or driven by open-drain/open-collector logic. Minimum pulse width 1 µs; MR-to-reset delay ≤500 ns."+        "description": "Active-low manual reset input. Pulling this pin low triggers a reset pulse on both reset outputs. Internally pulled up to VCC via a ~50 k\u03a9 resistor (38-62 k\u03a9), so it can be left floating, driven by CMOS, or driven by open-drain/open-collector logic. Minimum pulse width 1 \u00b5s; MR-to-reset delay \u2264500 ns."       },       {         "number": "2",@@ -44,25 +46,25 @@         "number": "3",         "name": "/RESET",         "type": "output",-        "description": "Active-low reset output. Driven low when VCC is below the 2.63 V reset threshold, when /MR is low, or when the watchdog times out. After the condition clears, /RESET stays low for at least 140 ms (typ. 200 ms) before returning high. VOL = 0.3 V max at 3.2 mA sink (150 µA at VCC = 1.1 V)."+        "description": "Active-low reset output. Driven low when VCC is below the 2.63 V reset threshold, when /MR is low, or when the watchdog times out. After the condition clears, /RESET stays low for at least 140 ms (typ. 200 ms) before returning high. VOL = 0.3 V max at 3.2 mA sink (150 \u00b5A at VCC = 1.1 V)."       },       {         "number": "4",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply input, 1.1 V to 6.5 V operating range. This pin is continuously monitored and compared to the internal 2.63 V (CN825R) reset threshold. Supply current 2.7 µA typ. below threshold, 16 µA typ. above threshold. Abs max 6.5 V, 20 mA."+        "description": "Positive supply input, 1.1 V to 6.5 V operating range. This pin is continuously monitored and compared to the internal 2.63 V (CN825R) reset threshold. Supply current 2.7 \u00b5A typ. below threshold, 16 \u00b5A typ. above threshold. Abs max 6.5 V, 20 mA."       },       {         "number": "5",         "name": "RESET",         "type": "output",-        "description": "Active-high reset output. Driven high when VCC is below the reset threshold, when /MR is low, or when the watchdog times out. After the condition clears, RESET stays high for at least 140 ms (typ. 200 ms) before returning low. VOH = VCC−1 V min at 1 mA source (1.0 V min at VCC = 1.1 V, 8 µA)."+        "description": "Active-high reset output. Driven high when VCC is below the reset threshold, when /MR is low, or when the watchdog times out. After the condition clears, RESET stays high for at least 140 ms (typ. 200 ms) before returning low. VOH = VCC\u22121 V min at 1 mA source (1.0 V min at VCC = 1.1 V, 8 \u00b5A)."       },       {         "number": "6",         "name": "WDI",         "type": "input",-        "description": "Watchdog input. If WDI is held high or low for more than the watchdog timeout (typ. 1.6 s, min 0.95 s, max 2.25 s) without a logic transition, the watchdog expires and asserts both reset outputs for ≥140 ms. Input high threshold 0.75·VCC, low threshold 0.25·VCC; input current ±50 nA; minimum detectable pulse width 50 ns."+        "description": "Watchdog input. If WDI is held high or low for more than the watchdog timeout (typ. 1.6 s, min 0.95 s, max 2.25 s) without a logic transition, the watchdog expires and asserts both reset outputs for \u2265140 ms. Input high threshold 0.75\u00b7VCC, low threshold 0.25\u00b7VCC; input current \u00b150 nA; minimum detectable pulse width 50 ns."       }     ],     "provenance": {