CKS32F103C8T6

@@ -0,0 +1,97 @@+# CKS32F103C8T6++**CKS** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++CKS32F103C8T6 from CKS, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VBAT | power_in | Backup battery input, 1.8-3.6 V. Powers RTC, LSE 32 kHz oscillator and backup registers when VDD is absent. |+| 2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13; alt: TAMPER input, RTC alarm/second output. Supplied by the backup power switch - output limited to 2 MHz / 30 pF load and cannot source current (e.g. LED). |+| 3 | PC14-OSC32_IN | bidirectional | GPIO PC14; alt: LSE 32.768 kHz crystal input (OSC32_IN). Backup-domain pin with the same drive limits as PC13. |+| 4 | PC15-OSC32_OUT | bidirectional | GPIO PC15; alt: LSE 32.768 kHz crystal output (OSC32_OUT). Backup-domain pin with the same drive limits as PC13. |+| 5 | OSC_IN | input | HSE main crystal oscillator input (default after reset). Can be remapped to GPIO PD0 by software. |+| 6 | OSC_OUT | output | HSE main crystal oscillator output (default after reset). Can be remapped to GPIO PD1 by software. |+| 7 | NRST | bidirectional | Active-low bidirectional reset. Driven low by internal power-on/PVD reset sources; can also be pulled low externally to reset the MCU. |+| 8 | VSSA | power_in | Analog ground reference for ADC, PLL, RC oscillators and reset block. Must be tied to VSS. |+| 9 | VDDA | power_in | Analog supply, 2.0-3.6 V (≥2.4 V when ADC is used). Powers ADC, reset, RC oscillator and PLL analog sections. |+| 10 | PA0-WKUP | bidirectional | GPIO PA0; alt: WKUP wake-up, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR. |+| 11 | PA1 | bidirectional | GPIO PA1; alt: USART2_RTS, ADC12_IN1, TIM2_CH2. |+| 12 | PA2 | bidirectional | GPIO PA2; alt: USART2_TX, ADC12_IN2, TIM2_CH3. |+| 13 | PA3 | bidirectional | GPIO PA3; alt: USART2_RX, ADC12_IN3, TIM2_CH4. |+| 14 | PA4 | bidirectional | GPIO PA4; alt: SPI1_NSS, USART2_CK, ADC12_IN4. |+| 15 | PA5 | bidirectional | GPIO PA5; alt: SPI1_SCK, ADC12_IN5. |+| 16 | PA6 | bidirectional | GPIO PA6; alt: SPI1_MISO, ADC12_IN6, TIM3_CH1, TIM1_BKIN. |+| 17 | PA7 | bidirectional | GPIO PA7; alt: SPI1_MOSI, ADC12_IN7, TIM3_CH2, TIM1_CH1N. |+| 18 | PB0 | bidirectional | GPIO PB0; alt: ADC12_IN8, TIM3_CH3, TIM1_CH2N. |+| 19 | PB1 | bidirectional | GPIO PB1; alt: ADC12_IN9, TIM3_CH4, TIM1_CH3N. |+| 20 | PB2/BOOT1 | bidirectional | GPIO PB2, 5 V tolerant. Also samples BOOT1 at reset (with BOOT0) to select the boot memory (main flash / system memory / SRAM). |+| 21 | PB10 | bidirectional | GPIO PB10, 5 V tolerant; alt: I2C2_SCL, USART3_TX, TIM2_CH3. |+| 22 | PB11 | bidirectional | GPIO PB11, 5 V tolerant; alt: I2C2_SDA, USART3_RX, TIM2_CH4. |+| 23 | VSS_1 | power_in | Digital ground. |+| 24 | VDD_1 | power_in | Digital supply, 2.0-3.6 V. Powers internal regulator and I/O. |+| 25 | PB12 | bidirectional | GPIO PB12, 5 V tolerant; alt: SPI2_NSS, I2C2_SMBA, USART3_CK, TIM1_BKIN. |+| 26 | PB13 | bidirectional | GPIO PB13, 5 V tolerant; alt: SPI2_SCK, USART3_CTS, TIM1_CH1N. |+| 27 | PB14 | bidirectional | GPIO PB14, 5 V tolerant; alt: SPI2_MISO, USART3_RTS, TIM1_CH2N. |+| 28 | PB15 | bidirectional | GPIO PB15, 5 V tolerant; alt: SPI2_MOSI, TIM1_CH3N. |+| 29 | PA8 | bidirectional | GPIO PA8, 5 V tolerant; alt: USART1_CK, TIM1_CH1, MCO (master clock output). |+| 30 | PA9 | bidirectional | GPIO PA9, 5 V tolerant; alt: USART1_TX, TIM1_CH2. |+| 31 | PA10 | bidirectional | GPIO PA10, 5 V tolerant; alt: USART1_RX, TIM1_CH3. |+| 32 | PA11 | bidirectional | GPIO PA11, 5 V tolerant; alt: USART1_CTS, USBDM, CAN_RX, TIM1_CH4. |+| 33 | PA12 | bidirectional | GPIO PA12, 5 V tolerant; alt: USART1_RTS, USBDP, CAN_TX, TIM1_ETR. |+| 34 | PA13 | bidirectional | JTMS/SWDIO after reset (default). Can be reassigned as GPIO PA13 by disabling JTAG/SWD debug via AFIO. |+| 35 | VSS_2 | power_in | Digital ground. |+| 36 | VDD_2 | power_in | Digital supply, 2.0-3.6 V. |+| 37 | PA14 | bidirectional | JTCK/SWCLK after reset (default). Can be reassigned as GPIO PA14 by disabling JTAG/SWD via AFIO. |+| 38 | PA15 | bidirectional | JTDI after reset (default). Can be released to GPIO PA15 (also TIM2_CH1_ETR, SPI1_NSS) by disabling JTAG via AFIO. |+| 39 | PB3 | bidirectional | JTDO after reset (default). Can be released to GPIO PB3 (also TRACESWO, TIM2_CH2, SPI1_SCK) by disabling JTAG via AFIO. |+| 40 | PB4 | bidirectional | JNTRST after reset (default). Can be released to GPIO PB4 (also TIM3_CH1, SPI1_MISO) by disabling JTAG via AFIO. |+| 41 | PB5 | bidirectional | GPIO PB5 (not 5 V tolerant); alt: I2C1_SMBA, TIM3_CH2, SPI1_MOSI. |+| 42 | PB6 | bidirectional | GPIO PB6, 5 V tolerant; alt: I2C1_SCL, TIM4_CH1, USART1_TX. |+| 43 | PB7 | bidirectional | GPIO PB7, 5 V tolerant; alt: I2C1_SDA, TIM4_CH2, USART1_RX. |+| 44 | BOOT0 | input | Boot mode select strap, sampled at reset. Together with BOOT1 (PB2) selects between main flash, system memory (bootloader) and embedded SRAM. |+| 45 | PB8 | bidirectional | GPIO PB8, 5 V tolerant; alt: I2C1_SCL (remap), TIM4_CH3, CAN_RX (remap). |+| 46 | PB9 | bidirectional | GPIO PB9, 5 V tolerant; alt: I2C1_SDA (remap), TIM4_CH4, CAN_TX (remap). |+| 47 | VSS_3 | power_in | Digital ground. |+| 48 | VDD_3 | power_in | Digital supply, 2.0-3.6 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | CKS |+| Package | LQFP-48(7x7) |+| Category | MCU |+| Pins | 48 |++## Ordering variants++- `CKS32F103C8T6`+- `CKS32F103C8T6CBT6`+- `CKS32F103C8T6C8U6`+- `CKS32F103C8T6CBU6`+- `CKS32F103C8T6R8T6`+- `CKS32F103C8T6RBT6`+- `CKS32F103C8T6V8T6`+- `CKS32F103C8T6VBT6`+- `CKS32F103C8T6T8U6`+- `CKS32F103C8T6TBU6`++## CAD (KiCad official)++- Symbol: `CKS32F103C8T6`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [CKS datasheet](docs/cks32f103c8t6-datasheet.pdf) (64 pp, sha256 `221001e6207f4f99`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cks32f103c8t6-datasheet.pdf)