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CDCVF25081PW
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CDCVF25081PW++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-16++CDCVF25081PW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLKIN | input | Clock input that must have a fixed frequency and phase for the PLL to acquire lock, and a stabilization time is required after power-up and valid signal application. |+| 2 | 1Y0 | output | Bank 1 Y0 clock output with an integrated 25-Ω series-damping resistor. |+| 3 | 1Y1 | output | Bank 1 Y1 clock output with an integrated 25-Ω series-damping resistor. |+| 4 | VDD | power_in | 3.3 V power supply for the output channels and core voltage (3 V to 3.6 V supply range per recommended operating conditions). |+| 5 | GND | power_in | Ground; connect to system ground. |+| 6 | 2Y0 | output | Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor. |+| 7 | 2Y1 | output | Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor. |+| 8 | S2 | input | Input selection pin that, together with S1, selects the input port and output source (PLL, bypassed PLL, or high-impedance) per Table 8-2. |+| 9 | S1 | input | Input selection pin that, together with S2, selects the input port and output source (PLL, bypassed PLL, or high-impedance) per Table 8-2. |+| 10 | 2Y2 | output | Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor. |+| 11 | 2Y3 | output | Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor. |+| 12 | GND | power_in | Ground; connect to system ground. |+| 13 | VDD | power_in | 3.3 V power supply for the output channels and core voltage (3 V to 3.6 V supply range per recommended operating conditions). |+| 14 | 1Y2 | output | Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor. |+| 15 | 1Y3 | output | Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor. |+| 16 | FBIN | input | Feedback input to the internal PLL that must be wired to one of the outputs to complete the feedback loop for zero-delay operation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Clock/Timing |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CDCVF25081PW`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cdcvf25081pw-etched.step` / `cdcvf25081pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcvf25081pw.step` / `cdcvf25081pw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdcvf25081.pdf) (26 pp, sha256 `9f846462bdac0c0a`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdcvf25081pw-datasheet.pdf)
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connect to system ground."+ },+ {+ "number": "6",+ "name": "2Y0",+ "type": "output",+ "description": "Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "7",+ "name": "2Y1",+ "type": "output",+ "description": "Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "8",+ "name": "S2",+ "type": "input",+ "description": "Input selection pin that, together with S1, selects the input port and output source (PLL, bypassed PLL, or high-impedance) per Table 8-2."+ },+ {+ "number": "9",+ "name": "S1",+ "type": "input",+ "description": "Input selection pin that, together with S2, selects the input port and output source (PLL, bypassed PLL, or high-impedance) per Table 8-2."+ },+ {+ "number": "10",+ "name": "2Y2",+ "type": "output",+ "description": "Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "11",+ "name": "2Y3",+ "type": "output",+ "description": "Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; connect to system ground."+ },+ {+ "number": "13",+ "name": "VDD",+ "type": "power_in",+ "description": "3.3 V power supply for the output channels and core voltage (3 V to 3.6 V supply range per recommended operating conditions)."+ },+ {+ "number": "14",+ "name": "1Y2",+ "type": "output",+ "description": "Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "15",+ "name": "1Y3",+ "type": "output",+ "description": "Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "16",+ "name": "FBIN",+ "type": "input",+ "description": "Feedback input to the internal PLL that must be wired to one of the outputs to complete the feedback loop for zero-delay operation."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 26,+ "cost_usd": 0.0887,+ "at": "2026-10-08T14:37:18"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cdcvf25081.pdf",+ "pages": 26,+ "sha256": "9f846462bdac0c0a",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdcvf25081pw.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdcvf25081pw-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "a1f3bb5d8c3213387a6e049012740c87f04ed5134e72b46061f255669061f301",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}