cdcvf2505dr

@@ -33,5 +33,79 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "CDCVF2505DR",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Clock Buffers, Drivers",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cdcvf2505.pdf",+    "parts": {+      "symbol": "cdcvf2505dr.kicad_sym",+      "footprint": "cdcvf2505dr.kicad_mod",+      "model_3d": "cdcvf2505dr-etched.glb",+      "model_3d_plain": "cdcvf2505dr.glb",+      "model_3d_step": "cdcvf2505dr-etched.step",+      "model_3d_step_plain": "cdcvf2505dr.step",+      "lbr": "cdcvf2505dr.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "CLKIN",+        "type": "input",+        "description": "Reference clock input to the integrated PLL. Must have a fixed frequency (24 MHz to 200 MHz) and fixed phase for the PLL to obtain phase lock; a 100 µs stabilization time is required after a valid signal is applied. High-impedance CMOS input (0.7·VDD/0.3·VDD thresholds)."+      },+      {+        "number": "2",+        "name": "1Y1",+        "type": "output",+        "description": "Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz)."+      },+      {+        "number": "3",+        "name": "1Y0",+        "type": "output",+        "description": "Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz)."+      },+      {+        "number": "4",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground reference. Provide a low-inductance, low-resistance connection to the reference plane."+      },+      {+        "number": "5",+        "name": "1Y2",+        "type": "output",+        "description": "Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz)."+      },+      {+        "number": "6",+        "name": "VDD",+        "type": "power_in",+        "description": "3.3-V supply (recommended 3.0-3.6 V; absolute max 4.3 V). Requires at least 100 nF local decoupling; a bank of 1 nF/2.2 nF/10 nF/47 nF/1 µF is recommended near the package."+      },+      {+        "number": "7",+        "name": "1Y3",+        "type": "output",+        "description": "Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz)."+      },+      {+        "number": "8",+        "name": "CLKOUT",+        "type": "output",+        "description": "Feedback output that closes the internal PLL loop; the feedback path is completed inside the chip and no external feedback wire is required. Can be loaded with a discrete capacitor (3-25 pF) to tune the phase relationship (zero delay, lead, or lag) between CLKIN and the 1Y[0-3] outputs. Not to be used to drive a signal trace."+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}