component
CDCVF2310PW
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+60@@ -0,0 +1,60 @@+# CDCVF2310PW++**Texas Instruments** · Clock Buffers, Drivers, Distributors · TSSOP-24++CDCVF2310PW from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground reference for the device. |+| 2 | VDD | power_in | DC power supply, 2.3 V to 3.6 V. |+| 3 | 1Y0 | output | Buffered output clock 0 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 4 | 1Y1 | output | Buffered output clock 1 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 5 | 1Y2 | output | Buffered output clock 2 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 6 | GND | power_in | Ground reference for the device. |+| 7 | GND | power_in | Ground reference for the device. |+| 8 | 1Y3 | output | Buffered output clock 3 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 9 | 1Y4 | output | Buffered output clock 4 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 10 | VDD | power_in | DC power supply, 2.3 V to 3.6 V. |+| 11 | 1G | input | Active-high output enable for 1Y[0:4]; outputs follow CLK when held high and are low when held low (glitch-suppressed relative to CLK falling edge). |+| 12 | 2Y4 | output | Buffered output clock 4 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 13 | 2G | input | Active-high output enable for 2Y[0:4]; outputs follow CLK when held high and are low when held low (glitch-suppressed relative to CLK falling edge). |+| 14 | VDD | power_in | DC power supply, 2.3 V to 3.6 V. |+| 15 | VDD | power_in | DC power supply, 2.3 V to 3.6 V. |+| 16 | 2Y3 | output | Buffered output clock 3 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 17 | 2Y2 | output | Buffered output clock 2 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 18 | GND | power_in | Ground reference for the device. |+| 19 | GND | power_in | Ground reference for the device. |+| 20 | 2Y1 | output | Buffered output clock 1 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 21 | 2Y0 | output | Buffered output clock 0 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins. |+| 22 | VDD | power_in | DC power supply, 2.3 V to 3.6 V. |+| 23 | VDD | power_in | DC power supply, 2.3 V to 3.6 V. |+| 24 | CLK | input | Input reference clock; the device operates up to 200 MHz at VDD = 3.3 V and up to 170 MHz at VDD = 2.3 V to 2.7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-24 |+| Category | Clock/Timing |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `CDCVF2310PW`+- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`+- 3D model: TSSOP-24 (KiCad packages3D, STEP)+- 3D model files: `cdcvf2310pw-etched.step` / `cdcvf2310pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcvf2310pw.step` / `cdcvf2310pw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdcvf2310.pdf) (25 pp, sha256 `ca9739d492358f80`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdcvf2310pw-datasheet.pdf)
page.jsonadded+296@@ -0,0 +1,296 @@+{+ "slug": "cdcvf2310pw",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cdcvf2310pw",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdcvf2310pw.kicad_sym",+ "cdcvf2310pw.kicad_mod",+ "cdcvf2310pw.glb",+ "cdcvf2310pw.step",+ "cdcvf2310pw.lbr",+ "docs/hero.png",+ "docs/cdcvf2310pw-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cdcvf2310pw-hero.glb",+ "cdcvf2310pw-hero.overlay.json"+ ],+ "component": {+ "mpn": "CDCVF2310PW",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-24",+ "pin_count": 24,+ "category": "Clock/Timing",+ "subcategory": "Clock Buffers, Drivers, Distributors",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cdcvf2310.pdf",+ "parts": {+ "symbol": "cdcvf2310pw.kicad_sym",+ "footprint": "cdcvf2310pw.kicad_mod",+ "model_3d": "cdcvf2310pw-hero.glb",+ "model_3d_plain": "cdcvf2310pw.glb",+ "model_3d_step": "cdcvf2310pw-etched.step",+ "model_3d_step_plain": "cdcvf2310pw.step",+ "lbr": "cdcvf2310pw.lbr"+ },+ "distributor_links": {+ "lcsc": "C1545794",+ "digikey": "2156-CDCVF2310PW-ND",+ "mouser": "595-CDCVF2310PW"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T22:02:43Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-CDCVF2310PW-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CDCVF2310PW",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "2",+ "name": "VDD",+ "type": "power_in",+ "description": "DC power supply, 2.3 V to 3.6 V."+ },+ {+ "number": "3",+ "name": "1Y0",+ "type": "output",+ "description": "Buffered output clock 0 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "4",+ "name": "1Y1",+ "type": "output",+ "description": "Buffered output clock 1 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "5",+ "name": "1Y2",+ "type": "output",+ "description": "Buffered output clock 2 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "6",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "8",+ "name": "1Y3",+ "type": "output",+ "description": "Buffered output clock 3 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "9",+ "name": "1Y4",+ "type": "output",+ "description": "Buffered output clock 4 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "10",+ "name": "VDD",+ "type": "power_in",+ "description": "DC power supply, 2.3 V to 3.6 V."+ },+ {+ "number": "11",+ "name": "1G",+ "type": "input",+ "description": "Active-high output enable for 1Y[0:4]; outputs follow CLK when held high and are low when held low (glitch-suppressed relative to CLK falling edge)."+ },+ {+ "number": "12",+ "name": "2Y4",+ "type": "output",+ "description": "Buffered output clock 4 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "13",+ "name": "2G",+ "type": "input",+ "description": "Active-high output enable for 2Y[0:4]; outputs follow CLK when held high and are low when held low (glitch-suppressed relative to CLK falling edge)."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "DC power supply, 2.3 V to 3.6 V."+ },+ {+ "number": "15",+ "name": "VDD",+ "type": "power_in",+ "description": "DC power supply, 2.3 V to 3.6 V."+ },+ {+ "number": "16",+ "name": "2Y3",+ "type": "output",+ "description": "Buffered output clock 3 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "17",+ "name": "2Y2",+ "type": "output",+ "description": "Buffered output clock 2 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "19",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "20",+ "name": "2Y1",+ "type": "output",+ "description": "Buffered output clock 1 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "21",+ "name": "2Y0",+ "type": "output",+ "description": "Buffered output clock 0 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins."+ },+ {+ "number": "22",+ "name": "VDD",+ "type": "power_in",+ "description": "DC power supply, 2.3 V to 3.6 V."+ },+ {+ "number": "23",+ "name": "VDD",+ "type": "power_in",+ "description": "DC power supply, 2.3 V to 3.6 V."+ },+ {+ "number": "24",+ "name": "CLK",+ "type": "input",+ "description": "Input reference clock; the device operates up to 200 MHz at VDD = 3.3 V and up to 170 MHz at VDD = 2.3 V to 2.7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The PDF text extraction lists the right-hand column (pins 24 to 13) in reverse order. Pin numbers we; The datasheet gives no separate description for the output pins beyond 'Buffered output clocks'. The; The schema has no spec field, so no headline electrical specs were returned. The datasheet gives VDD"+ ],+ "pages_sent": 25,+ "cost_usd": 0.0981,+ "at": "2026-10-07T22:02:22"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cdcvf2310.pdf",+ "pages": 25,+ "sha256": "ca9739d492358f80",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdcvf2310pw.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdcvf2310pw-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0e02a9a4f17c36de77758bd57dab69446c24f8403211a35e392671056f93b261",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}