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CDCM9102RHBR
Public Made by Adomby adom
Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-32-EP(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+76@@ -0,0 +1,76 @@+# CDCM9102RHBR++**Texas Instruments** · Clock Generators / Frequency Synthesizers / PLL · VQFN-32-EP(5x5)++CDCM9102RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD2 | power_in | Power supply for the OUT1 clock output port. Nominal 3.3 V (3.0-3.6 V). |+| 2 | OUT1N | output | Output 1 negative terminal of the differential 100 MHz clock output. Format (LVPECL / LVDS / LVCMOS / HCSL) is selected via OS0/OS1. |+| 3 | OUT1P | output | Output 1 positive terminal of the differential 100 MHz clock output. Format (LVPECL / LVDS / LVCMOS / HCSL) is selected via OS0/OS1. |+| 4 | VDD1 | power_in | Power supply for the OUT0 clock output port. Nominal 3.3 V (3.0-3.6 V). |+| 5 | OUT0N | output | Output 0 negative terminal of the differential 100 MHz clock output. Format (LVPECL / LVDS / LVCMOS / HCSL) is selected via OS0/OS1. |+| 6 | OUT0P | output | Output 0 positive terminal of the differential 100 MHz clock output. Format (LVPECL / LVDS / LVCMOS / HCSL) is selected via OS0/OS1. |+| 7 | OE | input | Output enable / shutdown control input. See Table 2 for polarity and behavior. (Datasheet type column shows 'O' but description labels it an input.) |+| 8 | NC | unconnected | No connection permitted. Leave floating. |+| 9 | VDD3 | power_in | Power supply for the low-noise clock generator. Nominal 3.3 V (3.0-3.6 V). |+| 10 | OS1 | input | Output format select control input (see Table 3). Combined with OS0 selects LVPECL / LVDS / LVCMOS / HCSL output format. |+| 11 | OS0 | input | Output format select control input (see Table 3). Combined with OS1 selects LVPECL / LVDS / LVCMOS / HCSL output format. |+| 12 | RESET | input | Device reset input, active-low (see Table 4). A capacitor from this pin to GND is recommended for proper startup timing. |+| 13 | NC | unconnected | No connection permitted. Leave floating. |+| 14 | GND | power_in | Power supply ground and thermal relief. |+| 15 | NC | unconnected | No connection permitted. Leave floating. |+| 16 | VDD4 | power_in | Power supply for the low-noise clock generator. Nominal 3.3 V (3.0-3.6 V). |+| 17 | REGCAP2 | passive | Capacitor for the internal regulator. Connect a 10 µF Y5V capacitor to GND. |+| 18 | VDD5 | power_in | Power supply for the low-noise clock generator. Nominal 3.3 V (3.0-3.6 V). |+| 19 | REGCAP1 | passive | Capacitor for the internal regulator. Connect a 10 µF Y5V capacitor to GND. |+| 20 | VDD6 | power_in | Power supply for the crystal oscillator input stage. Nominal 3.3 V (3.0-3.6 V). |+| 21 | XIN | input | Parallel-resonant crystal input, 25 MHz. Connect an external 25 MHz crystal between XIN and GND. |+| 22 | GND | power_in | Power supply ground and thermal relief. |+| 23 | OSCOUT | output | Buffered crystal oscillator output port (25 MHz). |+| 24 | NC | unconnected | No connection permitted. Leave floating. |+| 25 | NC | unconnected | No connection permitted. Leave floating. |+| 26 | NC | unconnected | No connection permitted. Leave floating. |+| 27 | NC | unconnected | No connection permitted. Leave floating. |+| 28 | NC | unconnected | No connection permitted. Leave floating. |+| 29 | NC | unconnected | No connection permitted. Leave floating. |+| 30 | NC | unconnected | No connection permitted. Leave floating. |+| 31 | NC | unconnected | No connection permitted. Leave floating. |+| 32 | NC | unconnected | No connection permitted. Leave floating. |+| 33 | GND | power_in | Thermal pad on the package underside. Must be soldered to the board GND plane for both electrical ground and thermal relief. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-32-EP(5x5) |+| Category | RTC |+| Pins | 33 |++## Ordering variants++Same part, different packaging or reel option.++- `CDCM9102RHBR`+- `CDCM9102RHBRRHBT`++## CAD (KiCad official)++- Symbol: `CDCM9102RHBR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](docs/cdcm9102rhbr-datasheet.pdf) (30 pp, sha256 `8dc946a83e7c594b`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdcm9102rhbr-datasheet.pdf)
page.jsonadded+34@@ -0,0 +1,34 @@+{+ "slug": "cdcm9102rhbr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rtc",+ "cdcm9102rhbr"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdcm9102rhbr.kicad_sym",+ "cdcm9102rhbr.kicad_mod",+ "cdcm9102rhbr.glb",+ "cdcm9102rhbr.step",+ "cdcm9102rhbr.lbr",+ "docs/hero.png",+ "docs/cdcm9102rhbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}