cdcm6208v1rgzr

@@ -33,5 +33,325 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "CDCM6208V1RGZR",+    "manufacturer": "Texas Instruments",+    "package": "VQFN-48-EP(7x7)",+    "pin_count": 49,+    "category": "Clock Generators / Frequency Synthesizers / PLL",+    "parts": {+      "symbol": "cdcm6208v1rgzr.kicad_sym",+      "footprint": "cdcm6208v1rgzr.kicad_mod",+      "model_3d": "cdcm6208v1rgzr-etched.glb",+      "model_3d_plain": "cdcm6208v1rgzr.glb",+      "model_3d_step": "cdcm6208v1rgzr-etched.step",+      "model_3d_step_plain": "cdcm6208v1rgzr.step",+      "lbr": "cdcm6208v1rgzr.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "SI_MODE0",+        "type": "input",+        "description": "Serial interface mode / pin-mode select bit 0. LVCMOS input with internal 50-kΩ pulldown. Combined with SI_MODE1: 00=SPI, 01=I2C, 10=Pin mode, 11=RESERVED."+      },+      {+        "number": "2",+        "name": "SDI/SDA/PIN1",+        "type": "bidirectional",+        "description": "Muxed serial data pin. SPI: SDI serial data input. I2C: SDA open-drain bidirectional data (requires external pull-up). Pin mode: PIN1 control input. LVCMOS input, no pull resistor."+      },+      {+        "number": "3",+        "name": "SDO/AD0/PIN2",+        "type": "bidirectional",+        "description": "Muxed pin. SPI: SDO serial data output. I2C: AD0 address offset bit 0 input. Pin mode: PIN2 control input. LVCMOS, no pull resistor."+      },+      {+        "number": "4",+        "name": "SCS/AD1/PIN3",+        "type": "input",+        "description": "Muxed pin. SPI: SCS latch-enable / chip-select. I2C: AD1 address offset bit 1 input. Pin mode: PIN3 control input. LVCMOS, no pull resistor."+      },+      {+        "number": "5",+        "name": "SCL/PIN4",+        "type": "input",+        "description": "Muxed pin. SPI/I2C: serial clock (SCL). Pin mode: PIN4 control input. LVCMOS, no pull resistor."+      },+      {+        "number": "6",+        "name": "REF_SEL",+        "type": "input",+        "description": "Manual reference-selection MUX for the PLL. LVCMOS with 50-kΩ pullup. 0 = select PRI_REF, 1 = select SEC_REF (when Reg 4.12 = 1 in SPI/I2C mode)."+      },+      {+        "number": "7",+        "name": "VDD_PRI_REF",+        "type": "power_in",+        "description": "Analog supply for the primary reference input buffer. Set to 1.8 V, 2.5 V, or 3.3 V (1.71 V-3.465 V range); may be tied to VDD_SEC_REF."+      },+      {+        "number": "8",+        "name": "PRI_REFP",+        "type": "input",+        "description": "Primary reference clock input, positive side. Universal input buffer (supports crystal, CML, LVPECL, LVDS, LVCMOS)."+      },+      {+        "number": "9",+        "name": "PRI_REFN",+        "type": "input",+        "description": "Primary reference clock input, negative side. Universal input buffer."+      },+      {+        "number": "10",+        "name": "VDD_SEC_REF",+        "type": "power_in",+        "description": "Analog supply for the secondary reference input buffer. 1.8 V / 2.5 V / 3.3 V; may be tied to VDD_PRI_REF, or to GND if the secondary buffer is disabled (Reg 4 bit 5 = 0)."+      },+      {+        "number": "11",+        "name": "SEC_REFP",+        "type": "input",+        "description": "Secondary reference clock input, positive side. Universal input buffer."+      },+      {+        "number": "12",+        "name": "SEC_REFN",+        "type": "input",+        "description": "Secondary reference clock input, negative side. Universal input buffer."+      },+      {+        "number": "13",+        "name": "VDD_Y0_Y1",+        "type": "power_in",+        "description": "Analog output supply for clock outputs Y0 and Y1. Set independently to 1.8 V, 2.5 V, or 3.3 V (one of two supply pins for the Y0/Y1 pair)."+      },+      {+        "number": "14",+        "name": "Y0_P",+        "type": "output",+        "description": "Clock output 0, positive side. Universal output - configurable as LVPECL-like/normal-swing CML, LVDS-like CML, HCSL, or paired LVCMOS. Fractional divider available."+      },+      {+        "number": "15",+        "name": "Y0_N",+        "type": "output",+        "description": "Clock output 0, negative side. Universal output (see Y0_P)."+      },+      {+        "number": "16",+        "name": "Y1_N",+        "type": "output",+        "description": "Clock output 1, negative side. Universal output."+      },+      {+        "number": "17",+        "name": "Y1_P",+        "type": "output",+        "description": "Clock output 1, positive side. Universal output. Fractional divider available."+      },+      {+        "number": "18",+        "name": "VDD_Y0_Y1",+        "type": "power_in",+        "description": "Second analog output supply pin for Y0/Y1. Same net as pin 13; 1.8 V / 2.5 V / 3.3 V."+      },+      {+        "number": "19",+        "name": "VDD_Y2_Y3",+        "type": "power_in",+        "description": "Analog output supply for clock outputs Y2 and Y3 (one of two supply pins for the pair). 1.8 V / 2.5 V / 3.3 V."+      },+      {+        "number": "20",+        "name": "Y2_P",+        "type": "output",+        "description": "Clock output 2, positive side. Universal output. Fractional divider available."+      },+      {+        "number": "21",+        "name": "Y2_N",+        "type": "output",+        "description": "Clock output 2, negative side. Universal output."+      },+      {+        "number": "22",+        "name": "Y3_N",+        "type": "output",+        "description": "Clock output 3, negative side. Universal output."+      },+      {+        "number": "23",+        "name": "Y3_P",+        "type": "output",+        "description": "Clock output 3, positive side. Universal output. Fractional divider available."+      },+      {+        "number": "24",+        "name": "VDD_Y2_Y3",+        "type": "power_in",+        "description": "Second analog output supply pin for Y2/Y3. Same net as pin 19."+      },+      {+        "number": "25",+        "name": "Y4_N",+        "type": "output",+        "description": "Clock output 4, negative side. Universal output (integer-only divider - no fractional)."+      },+      {+        "number": "26",+        "name": "Y4_P",+        "type": "output",+        "description": "Clock output 4, positive side. Universal output."+      },+      {+        "number": "27",+        "name": "VDD_Y4",+        "type": "power_in",+        "description": "Analog output supply for clock output Y4. 1.8 V / 2.5 V / 3.3 V."+      },+      {+        "number": "28",+        "name": "Y5_N",+        "type": "output",+        "description": "Clock output 5, negative side. Universal output (integer-only divider)."+      },+      {+        "number": "29",+        "name": "Y5_P",+        "type": "output",+        "description": "Clock output 5, positive side. Universal output."+      },+      {+        "number": "30",+        "name": "VDD_Y5",+        "type": "power_in",+        "description": "Analog output supply for clock output Y5. 1.8 V / 2.5 V / 3.3 V."+      },+      {+        "number": "31",+        "name": "VDD_Y6",+        "type": "power_in",+        "description": "Analog output supply for clock output Y6. 1.8 V / 2.5 V / 3.3 V."+      },+      {+        "number": "32",+        "name": "Y6_P",+        "type": "output",+        "description": "Clock output 6, positive side. Universal output."+      },+      {+        "number": "33",+        "name": "Y6_N",+        "type": "output",+        "description": "Clock output 6, negative side. Universal output."+      },+      {+        "number": "34",+        "name": "VDD_Y7",+        "type": "power_in",+        "description": "Analog output supply for clock output Y7. 1.8 V / 2.5 V / 3.3 V."+      },+      {+        "number": "35",+        "name": "Y7_P",+        "type": "output",+        "description": "Clock output 7, positive side. Universal output."+      },+      {+        "number": "36",+        "name": "Y7_N",+        "type": "output",+        "description": "Clock output 7, negative side. Universal output."+      },+      {+        "number": "37",+        "name": "VDD_PLL1",+        "type": "power_in",+        "description": "Analog PLL1 power-supply pin. 1.8 V / 2.5 V / 3.3 V; noise-sensitive analog supply."+      },+      {+        "number": "38",+        "name": "VDD_PLL2",+        "type": "power_in",+        "description": "Analog PLL2 power-supply pin. Noise-sensitive; may be tied to VDD_VCO (both are analog supplies)."+      },+      {+        "number": "39",+        "name": "VDD_VCO",+        "type": "power_in",+        "description": "Analog PLL/VCO supply. Very noise-sensitive; typically tied to VDD_PLL2. 1.8 V / 2.5 V / 3.3 V."+      },+      {+        "number": "40",+        "name": "REG_CAP",+        "type": "passive",+        "description": "Internal regulator decoupling capacitor pin. Connect a 10-µF cap with ESR < 1 Ω (above 100 kHz) to GND."+      },+      {+        "number": "41",+        "name": "ELF",+        "type": "passive",+        "description": "External loop-filter pin for the PLL. Analog."+      },+      {+        "number": "42",+        "name": "SYNCN",+        "type": "input",+        "description": "Output sync input, active low. LVCMOS with 50-kΩ pullup. Outputs are synchronized on a low-to-high transition; held low, all outputs are disabled."+      },+      {+        "number": "43",+        "name": "PDN",+        "type": "input",+        "description": "Power-down, active low. LVCMOS with 50-kΩ pullup. PDN=VIH: normal operation. PDN=VIL: device disabled, minimum current; exit resets all registers. Recommended to add a cap to GND to hold device down during supply ramp."+      },+      {+        "number": "44",+        "name": "RESETN/PWR",+        "type": "input",+        "description": "Muxed pin. SPI/I2C modes: active-low RESETN (VIL = reset with register retention, VIH = active). Pin mode: PWR - selects core/IO supply voltage (0 = 1.8 V; 1 = 2.5 V / 3.3 V). LVCMOS with 50-kΩ pullup."+      },+      {+        "number": "45",+        "name": "STATUS1/PIN0",+        "type": "bidirectional",+        "description": "Muxed pin, no pull resistor. SPI/I2C mode: STATUS1 output (see Table 10/12). Pin mode: PIN0 control input."+      },+      {+        "number": "46",+        "name": "STATUS0",+        "type": "output",+        "description": "Status output 0. LVCMOS. Reports device status per Table 12."+      },+      {+        "number": "47",+        "name": "SI_MODE1",+        "type": "input",+        "description": "Serial-interface mode / pin-mode select bit 1. LVCMOS with 50-kΩ pullup. Combined with SI_MODE0: 00=SPI, 01=I2C, 10=Pin mode, 11=RESERVED."+      },+      {+        "number": "48",+        "name": "DVDD",+        "type": "power_in",+        "description": "Digital power supply. Also the reference supply voltage for all LVCMOS control inputs - must match expected input signal swing. 1.71 V-3.465 V (nominal 1.8/2.5/3.3 V)."+      },+      {+        "number": "PAD",+        "name": "GND",+        "type": "power_in",+        "description": "Exposed thermal pad on the underside of the VQFN package. Serves as the device ground return and primary thermal path - connect to the PCB ground plane with a via array (datasheet recommends 36 thermal vias, 0.3-mm diameter).",+        "thermal_pad": true+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}