cdcm6208v1rgzr

@@ -0,0 +1,90 @@+# CDCM6208V1RGZR++**Texas Instruments** · Clock Generators / Frequency Synthesizers / PLL · VQFN-48-EP(7x7)++CDCM6208V1RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SI_MODE0 | input | Serial interface mode / pin-mode select bit 0. LVCMOS input with internal 50-kΩ pulldown. Combined with SI_MODE1: 00=SPI, 01=I2C, 10=Pin mode, 11=RESERVED. |+| 2 | SDI/SDA/PIN1 | bidirectional | Muxed serial data pin. SPI: SDI serial data input. I2C: SDA open-drain bidirectional data (requires external pull-up). Pin mode: PIN1 control input. LVCMOS input, no pull resistor. |+| 3 | SDO/AD0/PIN2 | bidirectional | Muxed pin. SPI: SDO serial data output. I2C: AD0 address offset bit 0 input. Pin mode: PIN2 control input. LVCMOS, no pull resistor. |+| 4 | SCS/AD1/PIN3 | input | Muxed pin. SPI: SCS latch-enable / chip-select. I2C: AD1 address offset bit 1 input. Pin mode: PIN3 control input. LVCMOS, no pull resistor. |+| 5 | SCL/PIN4 | input | Muxed pin. SPI/I2C: serial clock (SCL). Pin mode: PIN4 control input. LVCMOS, no pull resistor. |+| 6 | REF_SEL | input | Manual reference-selection MUX for the PLL. LVCMOS with 50-kΩ pullup. 0 = select PRI_REF, 1 = select SEC_REF (when Reg 4.12 = 1 in SPI/I2C mode). |+| 7 | VDD_PRI_REF | power_in | Analog supply for the primary reference input buffer. Set to 1.8 V, 2.5 V, or 3.3 V (1.71 V-3.465 V range); may be tied to VDD_SEC_REF. |+| 8 | PRI_REFP | input | Primary reference clock input, positive side. Universal input buffer (supports crystal, CML, LVPECL, LVDS, LVCMOS). |+| 9 | PRI_REFN | input | Primary reference clock input, negative side. Universal input buffer. |+| 10 | VDD_SEC_REF | power_in | Analog supply for the secondary reference input buffer. 1.8 V / 2.5 V / 3.3 V; may be tied to VDD_PRI_REF, or to GND if the secondary buffer is disabled (Reg 4 bit 5 = 0). |+| 11 | SEC_REFP | input | Secondary reference clock input, positive side. Universal input buffer. |+| 12 | SEC_REFN | input | Secondary reference clock input, negative side. Universal input buffer. |+| 13 | VDD_Y0_Y1 | power_in | Analog output supply for clock outputs Y0 and Y1. Set independently to 1.8 V, 2.5 V, or 3.3 V (one of two supply pins for the Y0/Y1 pair). |+| 14 | Y0_P | output | Clock output 0, positive side. Universal output - configurable as LVPECL-like/normal-swing CML, LVDS-like CML, HCSL, or paired LVCMOS. Fractional divider available. |+| 15 | Y0_N | output | Clock output 0, negative side. Universal output (see Y0_P). |+| 16 | Y1_N | output | Clock output 1, negative side. Universal output. |+| 17 | Y1_P | output | Clock output 1, positive side. Universal output. Fractional divider available. |+| 18 | VDD_Y0_Y1 | power_in | Second analog output supply pin for Y0/Y1. Same net as pin 13; 1.8 V / 2.5 V / 3.3 V. |+| 19 | VDD_Y2_Y3 | power_in | Analog output supply for clock outputs Y2 and Y3 (one of two supply pins for the pair). 1.8 V / 2.5 V / 3.3 V. |+| 20 | Y2_P | output | Clock output 2, positive side. Universal output. Fractional divider available. |+| 21 | Y2_N | output | Clock output 2, negative side. Universal output. |+| 22 | Y3_N | output | Clock output 3, negative side. Universal output. |+| 23 | Y3_P | output | Clock output 3, positive side. Universal output. Fractional divider available. |+| 24 | VDD_Y2_Y3 | power_in | Second analog output supply pin for Y2/Y3. Same net as pin 19. |+| 25 | Y4_N | output | Clock output 4, negative side. Universal output (integer-only divider - no fractional). |+| 26 | Y4_P | output | Clock output 4, positive side. Universal output. |+| 27 | VDD_Y4 | power_in | Analog output supply for clock output Y4. 1.8 V / 2.5 V / 3.3 V. |+| 28 | Y5_N | output | Clock output 5, negative side. Universal output (integer-only divider). |+| 29 | Y5_P | output | Clock output 5, positive side. Universal output. |+| 30 | VDD_Y5 | power_in | Analog output supply for clock output Y5. 1.8 V / 2.5 V / 3.3 V. |+| 31 | VDD_Y6 | power_in | Analog output supply for clock output Y6. 1.8 V / 2.5 V / 3.3 V. |+| 32 | Y6_P | output | Clock output 6, positive side. Universal output. |+| 33 | Y6_N | output | Clock output 6, negative side. Universal output. |+| 34 | VDD_Y7 | power_in | Analog output supply for clock output Y7. 1.8 V / 2.5 V / 3.3 V. |+| 35 | Y7_P | output | Clock output 7, positive side. Universal output. |+| 36 | Y7_N | output | Clock output 7, negative side. Universal output. |+| 37 | VDD_PLL1 | power_in | Analog PLL1 power-supply pin. 1.8 V / 2.5 V / 3.3 V; noise-sensitive analog supply. |+| 38 | VDD_PLL2 | power_in | Analog PLL2 power-supply pin. Noise-sensitive; may be tied to VDD_VCO (both are analog supplies). |+| 39 | VDD_VCO | power_in | Analog PLL/VCO supply. Very noise-sensitive; typically tied to VDD_PLL2. 1.8 V / 2.5 V / 3.3 V. |+| 40 | REG_CAP | passive | Internal regulator decoupling capacitor pin. Connect a 10-µF cap with ESR < 1 Ω (above 100 kHz) to GND. |+| 41 | ELF | passive | External loop-filter pin for the PLL. Analog. |+| 42 | SYNCN | input | Output sync input, active low. LVCMOS with 50-kΩ pullup. Outputs are synchronized on a low-to-high transition; held low, all outputs are disabled. |+| 43 | PDN | input | Power-down, active low. LVCMOS with 50-kΩ pullup. PDN=VIH: normal operation. PDN=VIL: device disabled, minimum current; exit resets all registers. Recommended to add a cap to GND to hold device down during supply ramp. |+| 44 | RESETN/PWR | input | Muxed pin. SPI/I2C modes: active-low RESETN (VIL = reset with register retention, VIH = active). Pin mode: PWR - selects core/IO supply voltage (0 = 1.8 V; 1 = 2.5 V / 3.3 V). LVCMOS with 50-kΩ pullup. |+| 45 | STATUS1/PIN0 | bidirectional | Muxed pin, no pull resistor. SPI/I2C mode: STATUS1 output (see Table 10/12). Pin mode: PIN0 control input. |+| 46 | STATUS0 | output | Status output 0. LVCMOS. Reports device status per Table 12. |+| 47 | SI_MODE1 | input | Serial-interface mode / pin-mode select bit 1. LVCMOS with 50-kΩ pullup. Combined with SI_MODE0: 00=SPI, 01=I2C, 10=Pin mode, 11=RESERVED. |+| 48 | DVDD | power_in | Digital power supply. Also the reference supply voltage for all LVCMOS control inputs - must match expected input signal swing. 1.71 V-3.465 V (nominal 1.8/2.5/3.3 V). |+| PAD | GND | power_in | Exposed thermal pad on the underside of the VQFN package. Serves as the device ground return and primary thermal path - connect to the PCB ground plane with a via array (datasheet recommends 36 thermal vias, 0.3-mm diameter). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | RTC |+| Pins | 49 |++## Ordering variants++- `CDCM6208V1RGZR`+- `CDCM6208V1RGZRRGZT`++## CAD (KiCad official)++- Symbol: `CDCM6208V1RGZR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](docs/cdcm6208v1rgzr-datasheet.pdf) (None pp, sha256 `0a8c01ef484475ad`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdcm6208v1rgzr-datasheet.pdf)