cdcm61002rhbr

@@ -33,5 +33,229 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "CDCM61002RHBR",+    "manufacturer": "Texas Instruments",+    "package": "VQFN-32-EP(5x5)",+    "pin_count": 33,+    "category": "Clock Generators / Frequency Synthesizers / PLL",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cdcm61002rhbr.pdf",+    "parts": {+      "symbol": "cdcm61002rhbr.kicad_sym",+      "footprint": "cdcm61002rhbr.kicad_mod",+      "model_3d": "cdcm61002rhbr-etched.glb",+      "model_3d_plain": "cdcm61002rhbr.glb",+      "model_3d_step": "cdcm61002rhbr-etched.step",+      "model_3d_step_plain": "cdcm61002rhbr.step",+      "lbr": "cdcm61002rhbr.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "VCC_OUT",+        "type": "power_in",+        "description": "3.3-V supply for the output buffers (3.0-3.6 V). Bypass to GND close to the pin."+      },+      {+        "number": "2",+        "name": "OUTN1",+        "type": "output",+        "description": "Universal output channel 1, negative leg. Forms a differential pair with OUTP1 (LVPECL/LVDS) or acts as an independent LVCMOS output depending on OS[1:0]."+      },+      {+        "number": "3",+        "name": "OUTP1",+        "type": "output",+        "description": "Universal output channel 1, positive leg. Forms a differential pair with OUTN1 (LVPECL/LVDS) or acts as an independent LVCMOS output depending on OS[1:0]."+      },+      {+        "number": "4",+        "name": "VCC_OUT",+        "type": "power_in",+        "description": "3.3-V supply for the output buffers (3.0-3.6 V). Second VCC_OUT pin; bypass to GND close to the pin."+      },+      {+        "number": "5",+        "name": "OUTN0",+        "type": "output",+        "description": "Universal output channel 0, negative leg. Forms a differential pair with OUTP0 (LVPECL/LVDS) or acts as an independent LVCMOS output depending on OS[1:0]."+      },+      {+        "number": "6",+        "name": "OUTP0",+        "type": "output",+        "description": "Universal output channel 0, positive leg. Forms a differential pair with OUTN0 (LVPECL/LVDS) or acts as an independent LVCMOS output depending on OS[1:0]."+      },+      {+        "number": "7",+        "name": "CE",+        "type": "input",+        "description": "Chip Enable control pin (3.3-V LVCMOS). CE=1 places the device in normal operation; CE=0 powers the outputs down (Hi-Z). Internal 150 kΩ pull-up."+      },+      {+        "number": "8",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. Leave floating or tie to GND."+      },+      {+        "number": "9",+        "name": "VCC_VCO",+        "type": "power_in",+        "description": "3.3-V supply for the internal LC-based VCO (3.0-3.6 V). Requires clean bypassing for low phase noise."+      },+      {+        "number": "10",+        "name": "OS1",+        "type": "input",+        "description": "Output type select bit 1 (3.3-V LVCMOS). Together with OS0 selects LVCMOS, LVDS, or LVPECL on the universal outputs and enables/disables OSC_OUT (see Table 6). Internal 150 kΩ pull-up."+      },+      {+        "number": "11",+        "name": "OS0",+        "type": "input",+        "description": "Output type select bit 0 (3.3-V LVCMOS). Together with OS1 selects LVCMOS, LVDS, or LVPECL on the universal outputs and enables/disables OSC_OUT (see Table 6). Internal 150 kΩ pull-up."+      },+      {+        "number": "12",+        "name": "RSTN",+        "type": "input",+        "description": "Active-low device reset / PLL recalibration trigger (3.3-V LVCMOS). Must be pulsed low then high after any change to PLL settings. Internal 150 kΩ pull-up."+      },+      {+        "number": "13",+        "name": "OD0",+        "type": "input",+        "description": "Output divider select bit 0 (3.3-V LVCMOS). OD[2:0] selects the shared output divider ratio 1/2/3/4/6/8 (see Table 5). Internal 150 kΩ pull-up."+      },+      {+        "number": "14",+        "name": "OD1",+        "type": "input",+        "description": "Output divider select bit 1 (3.3-V LVCMOS). OD[2:0] selects the shared output divider ratio 1/2/3/4/6/8 (see Table 5). Internal 150 kΩ pull-up."+      },+      {+        "number": "15",+        "name": "OD2",+        "type": "input",+        "description": "Output divider select bit 2 (3.3-V LVCMOS). OD[2:0] selects the shared output divider ratio 1/2/3/4/6/8 (see Table 5). Internal 150 kΩ pull-up."+      },+      {+        "number": "16",+        "name": "VCC_PLL2",+        "type": "power_in",+        "description": "3.3-V supply for the PLL circuitry (3.0-3.6 V). Requires clean bypassing for low phase noise."+      },+      {+        "number": "17",+        "name": "REG_CAP2",+        "type": "passive",+        "description": "Internal regulator bypass node. Connect a 10-μF Y5V capacitor from this pin to GND; do not drive externally."+      },+      {+        "number": "18",+        "name": "VCC_PLL1",+        "type": "power_in",+        "description": "3.3-V supply for the PLL circuitry (3.0-3.6 V). Requires clean bypassing for low phase noise."+      },+      {+        "number": "19",+        "name": "REG_CAP1",+        "type": "passive",+        "description": "Internal regulator bypass node. Connect a 10-μF Y5V capacitor from this pin to GND; do not drive externally."+      },+      {+        "number": "20",+        "name": "VCC_IN",+        "type": "power_in",+        "description": "3.3-V supply for the input buffers (3.0-3.6 V). Bypass to GND close to the pin."+      },+      {+        "number": "21",+        "name": "XIN",+        "type": "input",+        "description": "Parallel-resonant crystal input, also usable as an LVCMOS reference input. Accepts a 21.875-28.47 MHz fundamental-mode crystal (ESR ≤50 Ω, on-chip load ~8-10 pF) or a single-ended LVCMOS clock."+      },+      {+        "number": "22",+        "name": "GND1",+        "type": "power_in",+        "description": "Additional device ground; internally shorted on-chip to the thermal pad GND. Must be tied to the board ground plane."+      },+      {+        "number": "23",+        "name": "OSC_OUT",+        "type": "output",+        "description": "Buffered LVCMOS bypass output of the crystal/input reference (21.875-28.47 MHz). Enabled only when OS[1:0] = 11 per Table 6; otherwise held off."+      },+      {+        "number": "24",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. Leave floating or tie to GND."+      },+      {+        "number": "25",+        "name": "PR0",+        "type": "input",+        "description": "Prescaler/feedback divider select bit 0 (3.3-V LVCMOS). PR[1:0] selects one of four prescaler/feedback pairs (3/24, 5/15, 3/25, 4/20) per Table 4. Internal 150 kΩ pull-up."+      },+      {+        "number": "26",+        "name": "PR1",+        "type": "input",+        "description": "Prescaler/feedback divider select bit 1 (3.3-V LVCMOS). PR[1:0] selects one of four prescaler/feedback pairs (3/24, 5/15, 3/25, 4/20) per Table 4. Internal 150 kΩ pull-up."+      },+      {+        "number": "27",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. Leave floating or tie to GND."+      },+      {+        "number": "28",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. Leave floating or tie to GND."+      },+      {+        "number": "29",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. Leave floating or tie to GND."+      },+      {+        "number": "30",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. Leave floating or tie to GND."+      },+      {+        "number": "31",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. Leave floating or tie to GND."+      },+      {+        "number": "32",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. Leave floating or tie to GND."+      },+      {+        "number": "33",+        "name": "GND",+        "type": "power_in",+        "description": "Exposed thermal pad. Must be soldered to the board ground plane; serves as both the primary electrical ground and the primary thermal path (θJP ≈ 4 °C/W with 9 thermal vias)."+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}