component
CDCLVD1204RGTR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, QFN-16-EP(3x3). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+180−8@@ -1,13 +1,190 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cdclvd1204rgtr",+ "title": "CDCLVD1204RGTR",+ "brief": "Texas Instruments Clock Buffers, Drivers, Distributors, QFN-16-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Clock Buffers, Drivers, Distributors, QFN-16-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "clock-timing", "cdclvd1204rgtr" ],+ "component": {+ "mpn": "CDCLVD1204RGTR",+ "manufacturer": "Texas Instruments",+ "package": "QFN-16-EP(3x3)",+ "pin_count": 17,+ "category": "Clock/Timing",+ "subcategory": "Clock Buffers, Drivers, Distributors",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cdclvd1204.pdf",+ "parts": {+ "symbol": "cdclvd1204rgtr.kicad_sym",+ "footprint": "cdclvd1204rgtr.kicad_mod",+ "model_3d": "cdclvd1204rgtr.glb",+ "model_3d_step": "cdclvd1204rgtr.step",+ "lbr": "cdclvd1204rgtr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground."+ },+ {+ "number": "2",+ "name": "IN_SEL",+ "type": "input",+ "description": "Input selection with an internal 200-k\u03a9 pullup and pulldown; selects which input port (IN0 or IN1) is routed to the outputs. If left open (mid-level), outputs are disabled (static) for fail-safe operation."+ },+ {+ "number": "3",+ "name": "INP1",+ "type": "input",+ "description": "Positive side of differential clock input pair 1 (redundant input pair or single-ended input). Accepts LVDS, LVPECL, or LVCMOS up to 800 MHz differential."+ },+ {+ "number": "4",+ "name": "INN1",+ "type": "input",+ "description": "Negative side of differential clock input pair 1 (redundant input pair or single-ended input). When used single-ended, VAC_REF must be applied to this pin."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "2.5-V supply for the device (recommended range 2.375 V to 2.625 V)."+ },+ {+ "number": "6",+ "name": "INP0",+ "type": "input",+ "description": "Positive side of differential clock input pair 0 (redundant input pair or single-ended input). Accepts LVDS, LVPECL, or LVCMOS up to 800 MHz differential."+ },+ {+ "number": "7",+ "name": "INN0",+ "type": "input",+ "description": "Negative side of differential clock input pair 0 (redundant input pair or single-ended input). When used single-ended, VAC_REF must be applied to this pin."+ },+ {+ "number": "8",+ "name": "VAC_REF",+ "type": "output",+ "description": "Bias voltage output for capacitive-coupled inputs. TI recommends a 0.1-\u00b5F bypass capacitor from this pin to GND. Used to bias the unused negative input pin in single-ended input mode."+ },+ {+ "number": "9",+ "name": "OUTP0",+ "type": "output",+ "description": "Positive side of LVDS differential output pair 0 (ANSI EIA/TIA-644A compatible). Typical |VOD| = 250-450 mV into 100-\u03a9 differential load."+ },+ {+ "number": "10",+ "name": "OUTN0",+ "type": "output",+ "description": "Negative side of LVDS differential output pair 0 (ANSI EIA/TIA-644A compatible)."+ },+ {+ "number": "11",+ "name": "OUTP1",+ "type": "output",+ "description": "Positive side of LVDS differential output pair 1 (ANSI EIA/TIA-644A compatible)."+ },+ {+ "number": "12",+ "name": "OUTN1",+ "type": "output",+ "description": "Negative side of LVDS differential output pair 1 (ANSI EIA/TIA-644A compatible)."+ },+ {+ "number": "13",+ "name": "OUTP2",+ "type": "output",+ "description": "Positive side of LVDS differential output pair 2 (ANSI EIA/TIA-644A compatible)."+ },+ {+ "number": "14",+ "name": "OUTN2",+ "type": "output",+ "description": "Negative side of LVDS differential output pair 2 (ANSI EIA/TIA-644A compatible)."+ },+ {+ "number": "15",+ "name": "OUTP3",+ "type": "output",+ "description": "Positive side of LVDS differential output pair 3 (ANSI EIA/TIA-644A compatible)."+ },+ {+ "number": "16",+ "name": "OUTN3",+ "type": "output",+ "description": "Negative side of LVDS differential output pair 3 (ANSI EIA/TIA-644A compatible)."+ },+ {+ "number": "17",+ "name": "Thermal Pad",+ "type": "power_in",+ "description": "Exposed thermal pad on the bottom of the VQFN package. Must be soldered to the PCB ground plane for proper thermal and electrical performance."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cdclvd1204.pdf",+ "pages": 28,+ "sha256": "1218e131aa4118f0",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "QFN-16-EP(3x3)",+ "Category": "Clock/Timing",+ "Pins": "17"+ }+ },+ "variants": [+ {+ "mpn": "CDCLVD1204RGTR",+ "kind": "packaging"+ },+ {+ "mpn": "CDCLVD1204RGTRRGTT",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "cdclvd1204rgtr"+ ],+ "discovery_pitch": "CDCLVD1204RGTR (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +202,5 @@ "docs/cdclvd1204rgtr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }