component
CDC421A250RGER
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+61@@ -0,0 +1,61 @@+# CDC421A250RGER++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · VQFN-24-EP(4x4)++CDC421A250RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CE | input | Chip enable LVCMOS input: CE = 1 enables the device and outputs; CE = 0 disables all current sources so LVPECL outputs are Hi-Z. |+| 2 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 3 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 4 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 5 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 6 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 7 | OUTN | output | High-speed negative differential LVPECL output, enabled by the CE pin. |+| 8 | GND | power_in | Ground. |+| 9 | GND | power_in | Ground. |+| 10 | OUTP | output | High-speed positive differential LVPECL output, enabled by the CE pin. |+| 11 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 12 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 13 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 14 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 15 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 16 | VCC | power_in | 3.3-V power supply; recommended operating range 3.0 V to 3.6 V. |+| 17 | VCC | power_in | 3.3-V power supply; recommended operating range 3.0 V to 3.6 V. |+| 18 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 19 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 20 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 21 | XIN1 | input | In crystal mode, connect to one end of the crystal (XIN2 to the other end); in LVCMOS single-ended driven mode, this pin is the input reference. |+| 22 | XIN2 | input | In crystal mode, connect to the other end of the crystal; in LVCMOS single-ended driven mode, connect to GND. |+| 23 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 24 | NC | unconnected | TI test pin; do not connect, leave floating. |+| 25 | Thermal pad | passive | Exposed thermal pad on the package bottom; must be soldered to the PCB for thermal and mechanical performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-24-EP(4x4) |+| Category | Clock/Timing |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `CDC421A250RGER`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `cdc421a250rger-etched.step` / `cdc421a250rger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdc421a250rger.step` / `cdc421a250rger.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cdc421a100) (17 pp, sha256 `915ca5742046cc8c`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdc421a250rger-datasheet.pdf)
page.jsonadded+302@@ -0,0 +1,302 @@+{+ "slug": "cdc421a250rger",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cdc421a250rger",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdc421a250rger.kicad_sym",+ "cdc421a250rger.kicad_mod",+ "cdc421a250rger.glb",+ "cdc421a250rger.step",+ "cdc421a250rger.lbr",+ "docs/hero.png",+ "docs/cdc421a250rger-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cdc421a250rger-hero.glb",+ "cdc421a250rger-hero.overlay.json"+ ],+ "component": {+ "mpn": "CDC421A250RGER",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24-EP(4x4)",+ "pin_count": 25,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cdc421a100",+ "parts": {+ "symbol": "cdc421a250rger.kicad_sym",+ "footprint": "cdc421a250rger.kicad_mod",+ "model_3d": "cdc421a250rger-hero.glb",+ "model_3d_plain": "cdc421a250rger.glb",+ "model_3d_step": "cdc421a250rger-etched.step",+ "model_3d_step_plain": "cdc421a250rger.step",+ "lbr": "cdc421a250rger.lbr"+ },+ "distributor_links": {+ "lcsc": "C1537409",+ "digikey": "CDC421A250RGER-ND",+ "mouser": "595-CDC421A250RGER"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T19:14:47Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "CDC421A250RGER-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CDC421A250RGER",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CE",+ "type": "input",+ "description": "Chip enable LVCMOS input: CE = 1 enables the device and outputs; CE = 0 disables all current sources so LVPECL outputs are Hi-Z."+ },+ {+ "number": "2",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "4",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "6",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "7",+ "name": "OUTN",+ "type": "output",+ "description": "High-speed negative differential LVPECL output, enabled by the CE pin."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "9",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "10",+ "name": "OUTP",+ "type": "output",+ "description": "High-speed positive differential LVPECL output, enabled by the CE pin."+ },+ {+ "number": "11",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "12",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "13",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "14",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "15",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "3.3-V power supply; recommended operating range 3.0 V to 3.6 V."+ },+ {+ "number": "17",+ "name": "VCC",+ "type": "power_in",+ "description": "3.3-V power supply; recommended operating range 3.0 V to 3.6 V."+ },+ {+ "number": "18",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "19",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "20",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "21",+ "name": "XIN1",+ "type": "input",+ "description": "In crystal mode, connect to one end of the crystal (XIN2 to the other end); in LVCMOS single-ended driven mode, this pin is the input reference."+ },+ {+ "number": "22",+ "name": "XIN2",+ "type": "input",+ "description": "In crystal mode, connect to the other end of the crystal; in LVCMOS single-ended driven mode, connect to GND."+ },+ {+ "number": "23",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "24",+ "name": "NC",+ "type": "unconnected",+ "description": "TI test pin; do not connect, leave floating."+ },+ {+ "number": "25",+ "name": "Thermal pad",+ "type": "passive",+ "description": "Exposed thermal pad on the package bottom; must be soldered to the PCB for thermal and mechanical performance."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad is labeled pin 25 only in the package outline and land pattern drawings (pag; These 15 pins are NC in the pin table, described as TI test pins that must be left floating. They ar; XIN1 and XIN2 are typed as input, but the datasheet describes them as crystal terminals in crystal m"+ ],+ "pages_sent": 17,+ "cost_usd": 0.0945,+ "at": "2026-10-08T19:14:08"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cdc421a100",+ "pages": 17,+ "sha256": "915ca5742046cc8c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdc421a250rger.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f7d256794c4147daf24dcae0554fae18510315e565ad1e239b475be7fef80d8b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdc421a250rger-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7ae756d09d5e8153fe629b527fb4ac30e77e653cf6da0278b77e5719999d9de7",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}