component
CDC329AD
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CDC329AD++**Texas Instruments** · Clock Buffers, Drivers, Distributors · SOIC-16++CDC329AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground reference; the datasheet states distributed VCC and GND pins are used to reduce switching noise. |+| 2 | 1Y2 | output | Clock output 1Y2, which is true or complementary depending on the 1T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL. |+| 3 | 2Y1 | output | Clock output 2Y1, which is true or complementary depending on the 2T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL. |+| 4 | GND | power_in | Ground reference; the datasheet states distributed VCC and GND pins are used to reduce switching noise. |+| 5 | 2Y2 | output | Clock output 2Y2, which is true or complementary depending on the 2T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL. |+| 6 | 3Y | output | Clock output 3Y, which is true or complementary depending on the 3T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL. |+| 7 | GND | power_in | Ground reference; the datasheet states distributed VCC and GND pins are used to reduce switching noise. |+| 8 | 4Y | output | Clock output 4Y, which is true or complementary depending on the 4T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL. |+| 9 | 4T/C | input | Polarity-control input for output 4Y, TTL-compatible with VIH minimum 2 V and VIL maximum 0.8 V; selects true or complementary output polarity. |+| 10 | 3T/C | input | Polarity-control input for output 3Y, TTL-compatible with VIH minimum 2 V and VIL maximum 0.8 V; selects true or complementary output polarity. |+| 11 | VCC | power_in | Supply voltage, 4.75 V to 5.25 V recommended (5 V nominal); distributed VCC pins are used to reduce switching noise. |+| 12 | A | input | Clock input that is distributed to all six outputs; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input clock frequency up to 80 MHz. |+| 13 | 2T/C | input | Polarity-control input for outputs 2Y1 and 2Y2, TTL-compatible with VIH minimum 2 V and VIL maximum 0.8 V; selects true or complementary output polarity. |+| 14 | VCC | power_in | Supply voltage, 4.75 V to 5.25 V recommended (5 V nominal); distributed VCC pins are used to reduce switching noise. |+| 15 | 1T/C | input | Polarity-control input for outputs 1Y1 and 1Y2, TTL-compatible with VIH minimum 2 V and VIL maximum 0.8 V; selects true or complementary output polarity. |+| 16 | 1Y1 | output | Clock output 1Y1, which is true or complementary depending on the 1T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Clock/Timing |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CDC329AD`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cdc329ad-etched.step` / `cdc329ad-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdc329ad.step` / `cdc329ad.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cdc329a) (11 pp, sha256 `4b8e44ea2bef28a1`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdc329ad-datasheet.pdf)
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the datasheet states distributed VCC and GND pins are used to reduce switching noise."+ },+ {+ "number": "2",+ "name": "1Y2",+ "type": "output",+ "description": "Clock output 1Y2, which is true or complementary depending on the 1T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL."+ },+ {+ "number": "3",+ "name": "2Y1",+ "type": "output",+ "description": "Clock output 2Y1, which is true or complementary depending on the 2T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference; the datasheet states distributed VCC and GND pins are used to reduce switching noise."+ },+ {+ "number": "5",+ "name": "2Y2",+ "type": "output",+ "description": "Clock output 2Y2, which is true or complementary depending on the 2T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL."+ },+ {+ "number": "6",+ "name": "3Y",+ "type": "output",+ "description": "Clock output 3Y, which is true or complementary depending on the 3T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference; 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TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input clock frequency up to 80 MHz."+ },+ {+ "number": "13",+ "name": "2T/C",+ "type": "input",+ "description": "Polarity-control input for outputs 2Y1 and 2Y2, TTL-compatible with VIH minimum 2 V and VIL maximum 0.8 V; selects true or complementary output polarity."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 4.75 V to 5.25 V recommended (5 V nominal); distributed VCC pins are used to reduce switching noise."+ },+ {+ "number": "15",+ "name": "1T/C",+ "type": "input",+ "description": "Polarity-control input for outputs 1Y1 and 1Y2, TTL-compatible with VIH minimum 2 V and VIL maximum 0.8 V; selects true or complementary output polarity."+ },+ {+ "number": "16",+ "name": "1Y1",+ "type": "output",+ "description": "Clock output 1Y1, which is true or complementary depending on the 1T/C polarity-control input, with high drive of -32 mA IOH and 32 mA IOL."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 11,+ "cost_usd": 0.0702,+ "at": "2026-10-08T03:40:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cdc329a",+ "pages": 11,+ "sha256": "4b8e44ea2bef28a1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdc329ad.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdc329ad-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "1744a0ec1b03c6647d08f4c39195713859b8d9c8a5b2eea5270021d04586f52a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}