component
CD74HCT377M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# CD74HCT377M96++**Texas Instruments** · Flip Flops · SOIC-20-300mil++CD74HCT377M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | E | input | Active-low data enable input common to all eight flip-flops; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns before rising CP edge at VCC=4.5 V; presents 1.5 HCT unit loads (≤360 µA each at 25 °C). |+| 2 | Q0 | output | Registered Q output of flip-flop 0; assumes state of D0 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; propagation delay tPHL/tPLH ≤38 ns at CL=50 pF, VCC=4.5 V. |+| 3 | D0 | input | Data input for flip-flop 0; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; presents 0.25 HCT unit loads. |+| 4 | D1 | input | Data input for flip-flop 1; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; presents 0.25 HCT unit loads. |+| 5 | Q1 | output | Registered Q output of flip-flop 1; assumes state of D1 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature. |+| 6 | Q2 | output | Registered Q output of flip-flop 2; assumes state of D2 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; tPLH/tPHL ≤38 ns at CL=50 pF. |+| 7 | D2 | input | Data input for flip-flop 2; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V. |+| 8 | D3 | input | Data input for flip-flop 3; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ. |+| 9 | Q3 | output | Registered Q output of flip-flop 3; assumes state of D3 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; output transition time tTLH/tTHL ≤15 ns at CL=50 pF. |+| 10 | GND | power_in | Ground supply reference for all internal logic; DC GND current ICC/IGND must not exceed ±50 mA absolute maximum. |+| 11 | CP | input | Buffered clock input common to all eight flip-flops; flip-flops load on rising edge when E is Low; maximum clock frequency 25 MHz at VCC=4.5 V; clock pulse width tW ≥20 ns at VCC=4.5 V; presents 0.5 HCT unit loads. |+| 12 | Q7 | output | Registered Q output of flip-flop 7; assumes state of D7 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature. |+| 13 | D7 | input | Data input for flip-flop 7; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V. |+| 14 | D4 | input | Data input for flip-flop 4; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ. |+| 15 | Q4 | output | Registered Q output of flip-flop 4; assumes state of D4 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; tPLH/tPHL ≤38 ns at CL=50 pF. |+| 16 | Q6 | output | Registered Q output of flip-flop 6; assumes state of D6 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; output transition time tTLH/tTHL ≤15 ns at CL=50 pF. |+| 17 | D6 | input | Data input for flip-flop 6; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V. |+| 18 | D5 | input | Data input for flip-flop 5; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ. |+| 19 | Q5 | output | Registered Q output of flip-flop 5; assumes state of D5 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature. |+| 20 | VCC | power_in | Positive supply voltage for HCT type; operating range 4.5 V to 5.5 V; quiescent ICC ≤8 µA typ / 80 µA max at 25 °C; absolute maximum −0.5 V to 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `CD74HCT377M96`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `cd74hct377m96-etched.step` / `cd74hct377m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct377m96.step` / `cd74hct377m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct377) (20 pp, sha256 `e31605c6c3b60b6d`, retrieved 2026-09-24, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hct377m96-datasheet.pdf)
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VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns before rising CP edge at VCC=4.5 V; presents 1.5 HCT unit loads (≤360 µA each at 25 °C)."+ },+ {+ "number": "2",+ "name": "Q0",+ "type": "output",+ "description": "Registered Q output of flip-flop 0; assumes state of D0 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; propagation delay tPHL/tPLH ≤38 ns at CL=50 pF, VCC=4.5 V."+ },+ {+ "number": "3",+ "name": "D0",+ "type": "input",+ "description": "Data input for flip-flop 0; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; presents 0.25 HCT unit loads."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "input",+ "description": "Data input for flip-flop 1; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; presents 0.25 HCT unit loads."+ },+ {+ "number": "5",+ "name": "Q1",+ "type": "output",+ "description": "Registered Q output of flip-flop 1; assumes state of D1 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."+ },+ {+ "number": "6",+ "name": "Q2",+ "type": "output",+ "description": "Registered Q output of flip-flop 2; assumes state of D2 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; tPLH/tPHL ≤38 ns at CL=50 pF."+ },+ {+ "number": "7",+ "name": "D2",+ "type": "input",+ "description": "Data input for flip-flop 2; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V."+ },+ {+ "number": "8",+ "name": "D3",+ "type": "input",+ "description": "Data input for flip-flop 3; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."+ },+ {+ "number": "9",+ "name": "Q3",+ "type": "output",+ "description": "Registered Q output of flip-flop 3; assumes state of D3 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; output transition time tTLH/tTHL ≤15 ns at CL=50 pF."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground supply reference for all internal logic; DC GND current ICC/IGND must not exceed ±50 mA absolute maximum."+ },+ {+ "number": "11",+ "name": "CP",+ "type": "input",+ "description": "Buffered clock input common to all eight flip-flops; flip-flops load on rising edge when E is Low; maximum clock frequency 25 MHz at VCC=4.5 V; clock pulse width tW ≥20 ns at VCC=4.5 V; presents 0.5 HCT unit loads."+ },+ {+ "number": "12",+ "name": "Q7",+ "type": "output",+ "description": "Registered Q output of flip-flop 7; assumes state of D7 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."+ },+ {+ "number": "13",+ "name": "D7",+ "type": "input",+ "description": "Data input for flip-flop 7; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V."+ },+ {+ "number": "14",+ "name": "D4",+ "type": "input",+ "description": "Data input for flip-flop 4; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."+ },+ {+ "number": "15",+ "name": "Q4",+ "type": "output",+ "description": "Registered Q output of flip-flop 4; assumes state of D4 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; tPLH/tPHL ≤38 ns at CL=50 pF."+ },+ {+ "number": "16",+ "name": "Q6",+ "type": "output",+ "description": "Registered Q output of flip-flop 6; assumes state of D6 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; output transition time tTLH/tTHL ≤15 ns at CL=50 pF."+ },+ {+ "number": "17",+ "name": "D6",+ "type": "input",+ "description": "Data input for flip-flop 6; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V."+ },+ {+ "number": "18",+ "name": "D5",+ "type": "input",+ "description": "Data input for flip-flop 5; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."+ },+ {+ "number": "19",+ "name": "Q5",+ "type": "output",+ "description": "Registered Q output of flip-flop 5; assumes state of D5 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage for HCT type; operating range 4.5 V to 5.5 V; quiescent ICC ≤8 µA typ / 80 µA max at 25 °C; absolute maximum −0.5 V to 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 20,+ "cost_usd": 0.3518,+ "at": "2026-09-24T23:24:36"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hct377",+ "pages": 20,+ "sha256": "e31605c6c3b60b6d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}