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CD74HCT166M96
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Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# CD74HCT166M96++**Texas Instruments** · Shift Registers · SOIC-16++CD74HCT166M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SER | input | Serial data input, shifted into the first register stage on each clock rising edge when SH/LD is high. |+| 2 | A | input | Parallel data input A, loaded into the register when SH/LD is low. |+| 3 | B | input | Parallel data input B, loaded into the register when SH/LD is low. |+| 4 | C | input | Parallel data input C, loaded into the register when SH/LD is low. |+| 5 | D | input | Parallel data input D, loaded into the register when SH/LD is low. |+| 6 | CLK INH | input | Clock inhibit input, an active-low clock enable in the gated-OR clock structure; the CLK and CLK INH pin roles can be swapped for layout convenience. |+| 7 | CLK | input | Clock input, register advances on the low-to-high transition; HCT inputs are LSTTL-compatible (VIL 0.8 V max, VIH 2 V min). |+| 8 | GND | power_in | Ground, 0 V reference. |+| 9 | CLR | input | Active-low asynchronous clear that overrides all other inputs and forces all register bits low. |+| 10 | E | input | Parallel data input E, loaded into the register when SH/LD is low. |+| 11 | F | input | Parallel data input F, loaded into the register when SH/LD is low. |+| 12 | G | input | Parallel data input G, loaded into the register when SH/LD is low. |+| 13 | QH | output | Serial output from the last register stage (Q7); can drive the SER input of a succeeding stage. |+| 14 | H | input | Parallel data input H, loaded into the register when SH/LD is low. |+| 15 | SH/LD | input | Shift/load select: low loads parallel data on the clock edge, high enables serial shifting. |+| 16 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V for HCT types (absolute max 7 V); decouple with a 0.1 µF capacitor close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HCT166M96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hct166m96-etched.step` / `cd74hct166m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct166m96.step` / `cd74hct166m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc166) (24 pp, sha256 `79e283a5a2780469`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hct166m96-datasheet.pdf)
page.jsonadded+248@@ -0,0 +1,248 @@+{+ "slug": "cd74hct166m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hct166m96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hct166m96.kicad_sym",+ "cd74hct166m96.kicad_mod",+ "cd74hct166m96.glb",+ "cd74hct166m96.step",+ "cd74hct166m96.lbr",+ "docs/hero.png",+ "docs/cd74hct166m96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cd74hct166m96-hero.glb",+ "cd74hct166m96-hero.overlay.json"+ ],+ "component": {+ "mpn": "CD74HCT166M96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hc166",+ "parts": {+ "symbol": "cd74hct166m96.kicad_sym",+ "footprint": "cd74hct166m96.kicad_mod",+ "model_3d": "cd74hct166m96-hero.glb",+ "model_3d_plain": "cd74hct166m96.glb",+ "model_3d_step": "cd74hct166m96-etched.step",+ "model_3d_step_plain": "cd74hct166m96.step",+ "lbr": "cd74hct166m96.lbr"+ },+ "distributor_links": {+ "lcsc": "C2868525",+ "digikey": "296-49593-2-ND",+ "mouser": "595-CD74HCT166M96"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:50:25Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-49593-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74HCT166M96",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SER",+ "type": "input",+ "description": "Serial data input, shifted into the first register stage on each clock rising edge when SH/LD is high."+ },+ {+ "number": "2",+ "name": "A",+ "type": "input",+ "description": "Parallel data input A, loaded into the register when SH/LD is low."+ },+ {+ "number": "3",+ "name": "B",+ "type": "input",+ "description": "Parallel data input B, loaded into the register when SH/LD is low."+ },+ {+ "number": "4",+ "name": "C",+ "type": "input",+ "description": "Parallel data input C, loaded into the register when SH/LD is low."+ },+ {+ "number": "5",+ "name": "D",+ "type": "input",+ "description": "Parallel data input D, loaded into the register when SH/LD is low."+ },+ {+ "number": "6",+ "name": "CLK INH",+ "type": "input",+ "description": "Clock inhibit input, an active-low clock enable in the gated-OR clock structure; the CLK and CLK INH pin roles can be swapped for layout convenience."+ },+ {+ "number": "7",+ "name": "CLK",+ "type": "input",+ "description": "Clock input, register advances on the low-to-high transition; HCT inputs are LSTTL-compatible (VIL 0.8 V max, VIH 2 V min)."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground, 0 V reference."+ },+ {+ "number": "9",+ "name": "CLR",+ "type": "input",+ "description": "Active-low asynchronous clear that overrides all other inputs and forces all register bits low."+ },+ {+ "number": "10",+ "name": "E",+ "type": "input",+ "description": "Parallel data input E, loaded into the register when SH/LD is low."+ },+ {+ "number": "11",+ "name": "F",+ "type": "input",+ "description": "Parallel data input F, loaded into the register when SH/LD is low."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Parallel data input G, loaded into the register when SH/LD is low."+ },+ {+ "number": "13",+ "name": "QH",+ "type": "output",+ "description": "Serial output from the last register stage (Q7); can drive the SER input of a succeeding stage."+ },+ {+ "number": "14",+ "name": "H",+ "type": "input",+ "description": "Parallel data input H, loaded into the register when SH/LD is low."+ },+ {+ "number": "15",+ "name": "SH/LD",+ "type": "input",+ "description": "Shift/load select: low loads parallel data on the clock edge, high enables serial shifting."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 4.5 V to 5.5 V for HCT types (absolute max 7 V); decouple with a 0.1 µF capacitor close to the pin."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet has no text pin table for section 4; the pin layout was reconstructed from the scrambl; Pin 9 is labelled QH and pin 10 SER from the drawing text; the extraction order is ambiguous for the; Pin 15 is labelled CLR in the drawing but the functional text calls the input MR (controller reset)."+ ],+ "pages_sent": 24,+ "cost_usd": 0.1975,+ "at": "2026-10-08T18:49:53"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hc166",+ "pages": 24,+ "sha256": "79e283a5a2780469",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd74hct166m96.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd74hct166m96-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "65f5826f3151fc5982f5d3ffa0488feb871368b30d94a3da10f357d269da7bc8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}