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CD74HC595SM96
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Texas Instruments Shift Registers, SSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# CD74HC595SM96++**Texas Instruments** · Shift Registers · SSOP-16++CD74HC595SM96 from Texas Instruments, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | QB | tri_state | Storage register 3-state parallel output B, high-impedance when OE is high, with ±6mA drive at 5V. |+| 2 | QC | tri_state | Storage register 3-state parallel output C, high-impedance when OE is high, with ±6mA drive at 5V. |+| 3 | QD | tri_state | Storage register 3-state parallel output D, high-impedance when OE is high, with ±6mA drive at 5V. |+| 4 | QE | tri_state | Storage register 3-state parallel output E, high-impedance when OE is high, with ±6mA drive at 5V. |+| 5 | QF | tri_state | Storage register 3-state parallel output F, high-impedance when OE is high, with ±6mA drive at 5V. |+| 6 | QG | tri_state | Storage register 3-state parallel output G, high-impedance when OE is high, with ±6mA drive at 5V. |+| 7 | QH | tri_state | Storage register 3-state parallel output H, high-impedance when OE is high, with ±6mA drive at 5V. |+| 8 | GND | power_in | Ground pin; continuous current through VCC or GND is limited to ±70mA. |+| 9 | QH' | output | Serial output of the shift register for cascading, with 4mA drive at 4.5V. |+| 10 | SRCLR | input | Direct overriding clear for the shift register, active low. |+| 11 | SRCLK | input | Shift register clock, positive-edge triggered. |+| 12 | RCLK | input | Storage register clock, positive-edge triggered. |+| 13 | OE | input | Output enable; outputs QA-QH are in the high-impedance state when high and enabled when low. |+| 14 | SER | input | Serial data input to the shift register, sampled on the rising edge of SRCLK. |+| 15 | QA | tri_state | Storage register 3-state parallel output A, high-impedance when OE is high, with ±6mA drive at 5V. |+| 16 | VCC | power_in | Supply voltage, 2V to 6V recommended, absolute maximum 7V, with a 0.1-µF bypass capacitor recommended. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC595SM96`+- Footprint: `Package_SO:SSOP-16_5.3x6.2mm_P0.65mm`+- 3D model: SSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc595sm96-etched.step` / `cd74hc595sm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc595sm96.step` / `cd74hc595sm96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc595) (33 pp, sha256 `9ed505a61666567b`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc595sm96-datasheet.pdf)
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