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CD74HC299M96
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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# CD74HC299M96++**Texas Instruments** · Latches · SOIC-20-300mil++CD74HC299M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | S0 | input | Mode select input 0 which with S1 selects shift right, shift left, hold or parallel load, sampled on the low-to-high clock transition. |+| 2 | OE1 | input | Output enable 1; a high level on either OE1 or OE2 forces the I/O terminals to the off (high-impedance) state. |+| 3 | OE2 | input | Output enable 2; a high level on either OE1 or OE2 forces the I/O terminals to the off (high-impedance) state. |+| 4 | I/O6 | bidirectional | Three-state bus-drive parallel data input/output 6 (bus driver output, 15 LSTTL loads). |+| 5 | I/O4 | bidirectional | Three-state bus-drive parallel data input/output 4 (bus driver output, 15 LSTTL loads). |+| 6 | I/O2 | bidirectional | Three-state bus-drive parallel data input/output 2 (bus driver output, 15 LSTTL loads). |+| 7 | I/O0 | bidirectional | Three-state bus-drive parallel data input/output 0 (bus driver output, 15 LSTTL loads). |+| 8 | Q0 | output | Standard serial output from the first register stage (10 LSTTL loads), tied to DS7 of the preceding register when cascading. |+| 9 | MR | input | Asynchronous active-low master reset that clears the register regardless of all other inputs. |+| 10 | GND | power_in | Ground (0 V) supply pin. |+| 11 | DS0 | input | Serial data input for shift right, tied to Q7 of the preceding register when cascading. |+| 12 | CP | input | Clock pulse input; mode select and data are sampled on its low-to-high transition. |+| 13 | I/O1 | bidirectional | Three-state bus-drive parallel data input/output 1 (bus driver output, 15 LSTTL loads). |+| 14 | I/O3 | bidirectional | Three-state bus-drive parallel data input/output 3 (bus driver output, 15 LSTTL loads). |+| 15 | I/O5 | bidirectional | Three-state bus-drive parallel data input/output 5 (bus driver output, 15 LSTTL loads). |+| 16 | I/O7 | bidirectional | Three-state bus-drive parallel data input/output 7 (bus driver output, 15 LSTTL loads). |+| 17 | Q7 | output | Standard serial output from the last register stage (10 LSTTL loads), tied to DS0 of the following register when cascading. |+| 18 | DS7 | input | Serial data input for shift left, tied to Q0 of the following register when cascading. |+| 19 | S1 | input | Mode select input 1 which with S0 selects shift right, shift left, hold or parallel load; both high puts I/O in input mode. |+| 20 | VCC | power_in | Positive supply voltage, 2V to 6V for HC types (absolute maximum -0.5V to 7V). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic ICs |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `CD74HC299M96`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `cd74hc299m96-etched.step` / `cd74hc299m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc299m96.step` / `cd74hc299m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc299) (20 pp, sha256 `d3c541dfd0acb057`, retrieved 2026-10-01, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc299m96-datasheet.pdf)
page.jsonadded+228@@ -0,0 +1,228 @@+{+ "slug": "cd74hc299m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Latches, SOIC-20-300mil. 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a high level on either OE1 or OE2 forces the I/O terminals to the off (high-impedance) state."+ },+ {+ "number": "3",+ "name": "OE2",+ "type": "input",+ "description": "Output enable 2; a high level on either OE1 or OE2 forces the I/O terminals to the off (high-impedance) state."+ },+ {+ "number": "4",+ "name": "I/O6",+ "type": "bidirectional",+ "description": "Three-state bus-drive parallel data input/output 6 (bus driver output, 15 LSTTL loads)."+ },+ {+ "number": "5",+ "name": "I/O4",+ "type": "bidirectional",+ "description": "Three-state bus-drive parallel data input/output 4 (bus driver output, 15 LSTTL loads)."+ },+ {+ "number": "6",+ "name": "I/O2",+ "type": "bidirectional",+ "description": "Three-state bus-drive parallel data input/output 2 (bus driver output, 15 LSTTL loads)."+ },+ {+ "number": "7",+ "name": "I/O0",+ "type": "bidirectional",+ "description": "Three-state bus-drive parallel data input/output 0 (bus driver output, 15 LSTTL loads)."+ },+ {+ "number": "8",+ "name": "Q0",+ "type": "output",+ "description": "Standard serial output from the first register stage (10 LSTTL loads), tied to DS7 of the preceding register when cascading."+ },+ {+ "number": "9",+ "name": "MR",+ "type": "input",+ "description": "Asynchronous active-low master reset that clears the register regardless of all other inputs."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground (0 V) supply pin."+ },+ {+ "number": "11",+ "name": "DS0",+ "type": "input",+ "description": "Serial data input for shift right, tied to Q7 of the preceding register when cascading."+ },+ {+ "number": "12",+ "name": "CP",+ "type": "input",+ "description": "Clock pulse input; mode select and data are sampled on its low-to-high transition."+ },+ {+ "number": "13",+ "name": "I/O1",+ "type": "bidirectional",+ "description": "Three-state bus-drive parallel data input/output 1 (bus driver output, 15 LSTTL loads)."+ },+ {+ "number": "14",+ "name": "I/O3",+ "type": "bidirectional",+ "description": "Three-state bus-drive parallel data input/output 3 (bus driver output, 15 LSTTL loads)."+ },+ {+ "number": "15",+ "name": "I/O5",+ "type": "bidirectional",+ "description": "Three-state bus-drive parallel data input/output 5 (bus driver output, 15 LSTTL loads)."+ },+ {+ "number": "16",+ "name": "I/O7",+ "type": "bidirectional",+ "description": "Three-state bus-drive parallel data input/output 7 (bus driver output, 15 LSTTL loads)."+ },+ {+ "number": "17",+ "name": "Q7",+ "type": "output",+ "description": "Standard serial output from the last register stage (10 LSTTL loads), tied to DS0 of the following register when cascading."+ },+ {+ "number": "18",+ "name": "DS7",+ "type": "input",+ "description": "Serial data input for shift left, tied to Q0 of the following register when cascading."+ },+ {+ "number": "19",+ "name": "S1",+ "type": "input",+ "description": "Mode select input 1 which with S0 selects shift right, shift left, hold or parallel load; both high puts I/O in input mode."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, 2V to 6V for HC types (absolute maximum -0.5V to 7V)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 20,+ "cost_usd": 0.1418,+ "at": "2026-10-01T01:36:56"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hc299",+ "pages": 20,+ "sha256": "d3c541dfd0acb057",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}