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CD74HC20M
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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# CD74HC20M++**Texas Instruments** · Logic Gates · SOIC-14++CD74HC20M from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Channel 1 input A of the first 4-input NAND gate, which performs Y = A·B·C·D in positive logic; standard CMOS input with the input voltage range 0 to VCC. |+| 2 | 1B | input | Channel 1 input B of the first 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating. |+| 3 | NC | unconnected | Not internally connected. |+| 4 | 1C | input | Channel 1 input C of the first 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating. |+| 5 | 1D | input | Channel 1 input D of the first 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating. |+| 6 | 1Y | output | Channel 1 NAND output Y (Y = A·B·C·D) from a balanced CMOS push-pull output; output current is limited to ±25 mA continuous per the absolute maximum ratings. |+| 7 | GND | power_in | Ground reference for the device; continuous current through VCC or GND must not exceed ±50 mA. |+| 8 | 2Y | output | Channel 2 NAND output Y (Y = A·B·C·D) from a balanced CMOS push-pull output; output current is limited to ±25 mA continuous per the absolute maximum ratings. |+| 9 | 2A | input | Channel 2 input A of the second 4-input NAND gate; standard CMOS input with the input voltage range 0 to VCC. |+| 10 | 2B | input | Channel 2 input B of the second 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating. |+| 11 | NC | unconnected | Not internally connected. |+| 12 | 2C | input | Channel 2 input C of the second 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating. |+| 13 | 2D | input | Channel 2 input D of the second 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating. |+| 14 | VCC | power_in | Positive supply; recommended operating range is 2 V to 6 V, with an absolute maximum of 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD74HC20M`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `cd74hc20m-etched.step` / `cd74hc20m-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc20m.step` / `cd74hc20m.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc20) (27 pp, sha256 `3c399a095d2d45af`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc20m-datasheet.pdf)
page.jsonadded+237@@ -0,0 +1,237 @@+{+ "slug": "cd74hc20m",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hc20m",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hc20m.kicad_sym",+ "cd74hc20m.kicad_mod",+ "cd74hc20m.glb",+ "cd74hc20m.step",+ "cd74hc20m.lbr",+ "docs/hero.png",+ "docs/cd74hc20m-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cd74hc20m-hero.glb",+ "cd74hc20m-hero.overlay.json"+ ],+ "component": {+ "mpn": "CD74HC20M",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hc20",+ "parts": {+ "symbol": "cd74hc20m.kicad_sym",+ "footprint": "cd74hc20m.kicad_mod",+ "model_3d": "cd74hc20m-hero.glb",+ "model_3d_plain": "cd74hc20m.glb",+ "model_3d_step": "cd74hc20m-etched.step",+ "model_3d_step_plain": "cd74hc20m.step",+ "lbr": "cd74hc20m.lbr"+ },+ "distributor_links": {+ "lcsc": "C2863125",+ "digikey": "2156-CD74HC20M-HC-ND",+ "mouser": "595-CD74HC20M"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:32:19Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-CD74HC20M-HC-ND",+ "status": "found",+ "lifecycle": "Obsolete"+ },+ "mouser": {+ "pn": "595-CD74HC20M",+ "status": "found",+ "lifecycle": "End of Life"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1A",+ "type": "input",+ "description": "Channel 1 input A of the first 4-input NAND gate, which performs Y = A·B·C·D in positive logic; standard CMOS input with the input voltage range 0 to VCC."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Channel 1 input B of the first 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected."+ },+ {+ "number": "4",+ "name": "1C",+ "type": "input",+ "description": "Channel 1 input C of the first 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating."+ },+ {+ "number": "5",+ "name": "1D",+ "type": "input",+ "description": "Channel 1 input D of the first 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating."+ },+ {+ "number": "6",+ "name": "1Y",+ "type": "output",+ "description": "Channel 1 NAND output Y (Y = A·B·C·D) from a balanced CMOS push-pull output; output current is limited to ±25 mA continuous per the absolute maximum ratings."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device; continuous current through VCC or GND must not exceed ±50 mA."+ },+ {+ "number": "8",+ "name": "2Y",+ "type": "output",+ "description": "Channel 2 NAND output Y (Y = A·B·C·D) from a balanced CMOS push-pull output; output current is limited to ±25 mA continuous per the absolute maximum ratings."+ },+ {+ "number": "9",+ "name": "2A",+ "type": "input",+ "description": "Channel 2 input A of the second 4-input NAND gate; standard CMOS input with the input voltage range 0 to VCC."+ },+ {+ "number": "10",+ "name": "2B",+ "type": "input",+ "description": "Channel 2 input B of the second 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating."+ },+ {+ "number": "11",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected."+ },+ {+ "number": "12",+ "name": "2C",+ "type": "input",+ "description": "Channel 2 input C of the second 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating."+ },+ {+ "number": "13",+ "name": "2D",+ "type": "input",+ "description": "Channel 2 input D of the second 4-input NAND gate; unused inputs must be tied to VCC or GND and must not be left floating."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply; recommended operating range is 2 V to 6 V, with an absolute maximum of 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pin table (page 3) is for the D (SOIC-14) package and applies to CD74HC20M. The packag; The datasheet does not give a separate pinout for SOIC variants; the pinout shown is the single D/N/"+ ],+ "pages_sent": 27,+ "cost_usd": 0.0875,+ "at": "2026-10-08T16:32:01"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hc20",+ "pages": 27,+ "sha256": "3c399a095d2d45af",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd74hc20m.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd74hc20m-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "247c45a9609c8fbc280a7f19ab99e07a914ac466314eabdd4fa19c5dd6faee60",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}