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CD74HC195PWR
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Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD74HC195PWR++**Texas Instruments** · Shift Registers · TSSOP-16++CD74HC195PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MR | input | Asynchronous Master Reset, active low; a Low sets all Q outputs Low (Q3 bar High) independent of any other input. |+| 2 | J | input | Serial J input to the first stage, used when PE is High; tie to K for a D-type input. |+| 3 | K | input | Serial K input to the first stage, used when PE is High; tie to J for a D-type input. |+| 4 | D0 | input | Parallel data input 0, transferred to Q0 on the Low-to-High clock transition when PE is Low. |+| 5 | D1 | input | Parallel data input 1, transferred to Q1 on the Low-to-High clock transition when PE is Low. |+| 6 | D2 | input | Parallel data input 2, transferred to Q2 on the Low-to-High clock transition when PE is Low. |+| 7 | D3 | input | Parallel data input 3, transferred to Q3 on the Low-to-High clock transition when PE is Low. |+| 8 | GND | power_in | Ground (0V) supply pin. |+| 9 | PE | input | Parallel Enable; High selects shift right via J and K, Low selects parallel load from D0-D3 on the clock edge. |+| 10 | CP | input | Clock pulse input; all synchronous transfers occur on the Low-to-High transition. |+| 11 | Q3 bar | output | Complementary output of the last stage (inverse of Q3). |+| 12 | Q3 | output | Last-stage register output Q3. |+| 13 | Q2 | output | Register output Q2. |+| 14 | Q1 | output | Register output Q1. |+| 15 | Q0 | output | First-stage register output Q0. |+| 16 | VCC | power_in | Positive supply voltage, 2V to 6V for HC types (absolute max -0.5V to 7V). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC195PWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc195pwr-etched.step` / `cd74hc195pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc195pwr.step` / `cd74hc195pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hc195.pdf) (19 pp, sha256 `5004546e382e462d`, retrieved 2026-10-05, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc195pwr-datasheet.pdf)
page.jsonadded+208@@ -0,0 +1,208 @@+{+ "slug": "cd74hc195pwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hc195pwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hc195pwr.kicad_sym",+ "cd74hc195pwr.kicad_mod",+ "cd74hc195pwr.glb",+ "cd74hc195pwr.step",+ "cd74hc195pwr.lbr",+ "docs/hero.png",+ "docs/cd74hc195pwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cd74hc195pwr-hero.glb",+ "cd74hc195pwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "CD74HC195PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd74hc195.pdf",+ "parts": {+ "symbol": "cd74hc195pwr.kicad_sym",+ "footprint": "cd74hc195pwr.kicad_mod",+ "model_3d": "cd74hc195pwr-hero.glb",+ "model_3d_plain": "cd74hc195pwr.glb",+ "model_3d_step": "cd74hc195pwr-etched.step",+ "model_3d_step_plain": "cd74hc195pwr.step",+ "lbr": "cd74hc195pwr.lbr"+ },+ "distributor_links": {+ "lcsc": 2877048,+ "digikey": "296-CD74HC195PWRTR-ND",+ "mouser": "595-CD74HC195PWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T19:02:55Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-CD74HC195PWRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74HC195PWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "MR",+ "type": "input",+ "description": "Asynchronous Master Reset, active low; a Low sets all Q outputs Low (Q3 bar High) independent of any other input."+ },+ {+ "number": "2",+ "name": "J",+ "type": "input",+ "description": "Serial J input to the first stage, used when PE is High; tie to K for a D-type input."+ },+ {+ "number": "3",+ "name": "K",+ "type": "input",+ "description": "Serial K input to the first stage, used when PE is High; tie to J for a D-type input."+ },+ {+ "number": "4",+ "name": "D0",+ "type": "input",+ "description": "Parallel data input 0, transferred to Q0 on the Low-to-High clock transition when PE is Low."+ },+ {+ "number": "5",+ "name": "D1",+ "type": "input",+ "description": "Parallel data input 1, transferred to Q1 on the Low-to-High clock transition when PE is Low."+ },+ {+ "number": "6",+ "name": "D2",+ "type": "input",+ "description": "Parallel data input 2, transferred to Q2 on the Low-to-High clock transition when PE is Low."+ },+ {+ "number": "7",+ "name": "D3",+ "type": "input",+ "description": "Parallel data input 3, transferred to Q3 on the Low-to-High clock transition when PE is Low."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground (0V) supply pin."+ },+ {+ "number": "9",+ "name": "PE",+ "type": "input",+ "description": "Parallel Enable; High selects shift right via J and K, Low selects parallel load from D0-D3 on the clock edge."+ },+ {+ "number": "10",+ "name": "CP",+ "type": "input",+ "description": "Clock pulse input; all synchronous transfers occur on the Low-to-High transition."+ },+ {+ "number": "11",+ "name": "Q3 bar",+ "type": "output",+ "description": "Complementary output of the last stage (inverse of Q3)."+ },+ {+ "number": "12",+ "name": "Q3",+ "type": "output",+ "description": "Last-stage register output Q3."+ },+ {+ "number": "13",+ "name": "Q2",+ "type": "output",+ "description": "Register output Q2."+ },+ {+ "number": "14",+ "name": "Q1",+ "type": "output",+ "description": "Register output Q1."+ },+ {+ "number": "15",+ "name": "Q0",+ "type": "output",+ "description": "First-stage register output Q0."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, 2V to 6V for HC types (absolute max -0.5V to 7V)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 13 labeled as 'Q3' in datasheet is the inverted/complementary output from last stage (Q̄3), with"+ ],+ "pages_sent": 19,+ "cost_usd": 0.161,+ "at": "2026-10-05T19:02:38"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd74hc195.pdf",+ "pages": 19,+ "sha256": "5004546e382e462d",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}