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CD74HC173PWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD74HC173PWR++**Texas Instruments** · Flip Flops · TSSOP-16++CD74HC173PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | ~OE1 | input | Active-low output enable 1; when HIGH, all Q outputs are forced to the high-impedance (three-state) condition regardless of flip-flop state. |+| 2 | ~OE2 | input | Active-low output enable 2; when HIGH, all Q outputs are forced to the high-impedance (three-state) condition regardless of flip-flop state. |+| 3 | Q0 | tri_state | Three-state buffered output of flip-flop 0; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH. |+| 4 | Q1 | tri_state | Three-state buffered output of flip-flop 1; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH. |+| 5 | Q2 | tri_state | Three-state buffered output of flip-flop 2; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH. |+| 6 | Q3 | tri_state | Three-state buffered output of flip-flop 3; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH. |+| 7 | CP | input | Clock input (shared by all four flip-flops); data is captured on the positive-going edge; minimum clock pulse width 16 ns at VCC = 4.5 V, 85 °C. |+| 8 | GND | power_in | Ground supply reference; continuous current through GND pin must not exceed ±70 mA absolute maximum. |+| 9 | E1 | input | Data enable input 1; when HIGH, the Q output is fed back to the D input, forcing the flip-flop to retain its current state on the next clock edge. |+| 10 | E2 | input | Data enable input 2; when HIGH, the Q output is fed back to the D input, forcing the flip-flop to retain its current state on the next clock edge. |+| 11 | D3 | input | Data input for flip-flop 3; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V. |+| 12 | D2 | input | Data input for flip-flop 2; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V. |+| 13 | D1 | input | Data input for flip-flop 1; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V. |+| 14 | D0 | input | Data input for flip-flop 0; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V. |+| 15 | MR | input | Master reset, active HIGH and asynchronous; forces all Q outputs LOW independent of clock, E1, E2, and D inputs; tpd (MR to output) max 44 ns at VCC = 4.5 V, 85 °C. |+| 16 | VCC | power_in | Positive supply voltage; HC types 2 V to 6 V, HCT types 4.5 V to 5.5 V; absolute maximum 7 V; decouple with 0.1 µF ceramic capacitor placed as close to pin as possible. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC173PWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc173pwr-etched.step` / `cd74hc173pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc173pwr.step` / `cd74hc173pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hc173.pdf) (25 pp, sha256 `8e3cd2654a5626b0`, retrieved 2026-09-27, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (text+vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc173pwr-datasheet.pdf)
page.jsonadded+206@@ -0,0 +1,206 @@+{+ "slug": "cd74hc173pwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hc173pwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hc173pwr.kicad_sym",+ "cd74hc173pwr.kicad_mod",+ "cd74hc173pwr.glb",+ "cd74hc173pwr.step",+ "cd74hc173pwr.lbr",+ "docs/hero.png",+ "docs/cd74hc173pwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD74HC173PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd74hc173.pdf",+ "parts": {+ "symbol": "cd74hc173pwr.kicad_sym",+ "footprint": "cd74hc173pwr.kicad_mod",+ "model_3d": "cd74hc173pwr-etched.glb",+ "model_3d_plain": "cd74hc173pwr.glb",+ "model_3d_step": "cd74hc173pwr-etched.step",+ "model_3d_step_plain": "cd74hc173pwr.step",+ "lbr": "cd74hc173pwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C544791",+ "digikey": "296-12792-2-ND",+ "mouser": "595-CD74HC173PWR"+ },+ "distributor_check": {+ "checked_at": "2026-09-27T06:53:50Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-12792-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74HC173PWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "~OE1",+ "type": "input",+ "description": "Active-low output enable 1; when HIGH, all Q outputs are forced to the high-impedance (three-state) condition regardless of flip-flop state."+ },+ {+ "number": "2",+ "name": "~OE2",+ "type": "input",+ "description": "Active-low output enable 2; when HIGH, all Q outputs are forced to the high-impedance (three-state) condition regardless of flip-flop state."+ },+ {+ "number": "3",+ "name": "Q0",+ "type": "tri_state",+ "description": "Three-state buffered output of flip-flop 0; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH."+ },+ {+ "number": "4",+ "name": "Q1",+ "type": "tri_state",+ "description": "Three-state buffered output of flip-flop 1; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH."+ },+ {+ "number": "5",+ "name": "Q2",+ "type": "tri_state",+ "description": "Three-state buffered output of flip-flop 2; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH."+ },+ {+ "number": "6",+ "name": "Q3",+ "type": "tri_state",+ "description": "Three-state buffered output of flip-flop 3; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH."+ },+ {+ "number": "7",+ "name": "CP",+ "type": "input",+ "description": "Clock input (shared by all four flip-flops); data is captured on the positive-going edge; minimum clock pulse width 16 ns at VCC = 4.5 V, 85 °C."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground supply reference; continuous current through GND pin must not exceed ±70 mA absolute maximum."+ },+ {+ "number": "9",+ "name": "E1",+ "type": "input",+ "description": "Data enable input 1; when HIGH, the Q output is fed back to the D input, forcing the flip-flop to retain its current state on the next clock edge."+ },+ {+ "number": "10",+ "name": "E2",+ "type": "input",+ "description": "Data enable input 2; when HIGH, the Q output is fed back to the D input, forcing the flip-flop to retain its current state on the next clock edge."+ },+ {+ "number": "11",+ "name": "D3",+ "type": "input",+ "description": "Data input for flip-flop 3; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V."+ },+ {+ "number": "12",+ "name": "D2",+ "type": "input",+ "description": "Data input for flip-flop 2; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V."+ },+ {+ "number": "13",+ "name": "D1",+ "type": "input",+ "description": "Data input for flip-flop 1; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V."+ },+ {+ "number": "14",+ "name": "D0",+ "type": "input",+ "description": "Data input for flip-flop 0; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V."+ },+ {+ "number": "15",+ "name": "MR",+ "type": "input",+ "description": "Master reset, active HIGH and asynchronous; forces all Q outputs LOW independent of clock, E1, E2, and D inputs; tpd (MR to output) max 44 ns at VCC = 4.5 V, 85 °C."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; HC types 2 V to 6 V, HCT types 4.5 V to 5.5 V; absolute maximum 7 V; decouple with 0.1 µF ceramic capacitor placed as close to pin as possible."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-4-6",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-7",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 25,+ "cost_usd": 0.6222,+ "at": "2026-09-27T06:53:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd74hc173.pdf",+ "pages": 25,+ "sha256": "8e3cd2654a5626b0",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}