component
CD74HC173PWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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page.json+16−13@@ -65,37 +65,37 @@ "number": "3", "name": "Q0", "type": "tri_state",- "description": "Three-state buffered output of flip-flop 0; VOH \u2265 3.84 V and VOL \u2264 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 \u00b0C; high-impedance when OE1 or OE2 is HIGH."+ "description": "Three-state buffered output of flip-flop 0; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH." }, { "number": "4", "name": "Q1", "type": "tri_state",- "description": "Three-state buffered output of flip-flop 1; VOH \u2265 3.84 V and VOL \u2264 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 \u00b0C; high-impedance when OE1 or OE2 is HIGH."+ "description": "Three-state buffered output of flip-flop 1; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH." }, { "number": "5", "name": "Q2", "type": "tri_state",- "description": "Three-state buffered output of flip-flop 2; VOH \u2265 3.84 V and VOL \u2264 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 \u00b0C; high-impedance when OE1 or OE2 is HIGH."+ "description": "Three-state buffered output of flip-flop 2; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH." }, { "number": "6", "name": "Q3", "type": "tri_state",- "description": "Three-state buffered output of flip-flop 3; VOH \u2265 3.84 V and VOL \u2264 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 \u00b0C; high-impedance when OE1 or OE2 is HIGH."+ "description": "Three-state buffered output of flip-flop 3; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH = -6 mA / IOL = 6 mA, VCC = 4.5 V, 85 °C; high-impedance when OE1 or OE2 is HIGH." }, { "number": "7", "name": "CP", "type": "input",- "description": "Clock input (shared by all four flip-flops); data is captured on the positive-going edge; minimum clock pulse width 16 ns at VCC = 4.5 V, 85 \u00b0C."+ "description": "Clock input (shared by all four flip-flops); data is captured on the positive-going edge; minimum clock pulse width 16 ns at VCC = 4.5 V, 85 °C." }, { "number": "8", "name": "GND", "type": "power_in",- "description": "Ground supply reference; continuous current through GND pin must not exceed \u00b170 mA absolute maximum."+ "description": "Ground supply reference; continuous current through GND pin must not exceed ±70 mA absolute maximum." }, { "number": "9",@@ -113,37 +113,37 @@ "number": "11", "name": "D3", "type": "input",- "description": "Data input for flip-flop 3; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH \u2265 3.15 V, VIL \u2264 1.35 V at VCC = 4.5 V."+ "description": "Data input for flip-flop 3; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V." }, { "number": "12", "name": "D2", "type": "input",- "description": "Data input for flip-flop 2; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH \u2265 3.15 V, VIL \u2264 1.35 V at VCC = 4.5 V."+ "description": "Data input for flip-flop 2; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V." }, { "number": "13", "name": "D1", "type": "input",- "description": "Data input for flip-flop 1; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH \u2265 3.15 V, VIL \u2264 1.35 V at VCC = 4.5 V."+ "description": "Data input for flip-flop 1; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V." }, { "number": "14", "name": "D0", "type": "input",- "description": "Data input for flip-flop 0; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH \u2265 3.15 V, VIL \u2264 1.35 V at VCC = 4.5 V."+ "description": "Data input for flip-flop 0; sampled on the positive-going clock edge when E1 = LOW and E2 = LOW and MR = LOW; VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC = 4.5 V." }, { "number": "15", "name": "MR", "type": "input",- "description": "Master reset, active HIGH and asynchronous; forces all Q outputs LOW independent of clock, E1, E2, and D inputs; tpd (MR to output) max 44 ns at VCC = 4.5 V, 85 \u00b0C."+ "description": "Master reset, active HIGH and asynchronous; forces all Q outputs LOW independent of clock, E1, E2, and D inputs; tpd (MR to output) max 44 ns at VCC = 4.5 V, 85 °C." }, { "number": "16", "name": "VCC", "type": "power_in",- "description": "Positive supply voltage; HC types 2 V to 6 V, HCT types 4.5 V to 5.5 V; absolute maximum 7 V; decouple with 0.1 \u00b5F ceramic capacitor placed as close to pin as possible."+ "description": "Positive supply voltage; HC types 2 V to 6 V, HCT types 4.5 V to 5.5 V; absolute maximum 7 V; decouple with 0.1 µF ceramic capacitor placed as close to pin as possible." } ], "provenance": {@@ -223,5 +223,8 @@ "docs/cd74hc173pwr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }