component
CD74ACT374M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# CD74ACT374M96++**Texas Instruments** · Flip Flops · SOIC-20-300mil++CD74ACT374M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Output enable input; places Q outputs in high-impedance state when HIGH |+| 2 | 1Q | tri_state | Tristate output 1; set to D1 input level on positive clock edge when OE is LOW |+| 3 | 1D | input | Data input 1; captured into flip-flop 1 on LOW-to-HIGH clock transition |+| 4 | 2D | input | Data input 2; captured into flip-flop 2 on LOW-to-HIGH clock transition |+| 5 | 2Q | tri_state | Tristate output 2; set to D2 input level on positive clock edge when OE is LOW |+| 6 | 3Q | tri_state | Tristate output 3; set to D3 input level on positive clock edge when OE is LOW |+| 7 | 3D | input | Data input 3; captured into flip-flop 3 on LOW-to-HIGH clock transition |+| 8 | 4D | input | Data input 4; captured into flip-flop 4 on LOW-to-HIGH clock transition |+| 9 | 4Q | tri_state | Tristate output 4; set to D4 input level on positive clock edge when OE is LOW |+| 10 | GND | power_in | Ground reference potential |+| 11 | CLK | input | Clock input; positive transition captures data from D inputs into flip-flops |+| 12 | 5Q | tri_state | Tristate output 5; set to D5 input level on positive clock edge when OE is LOW |+| 13 | 5D | input | Data input 5; captured into flip-flop 5 on LOW-to-HIGH clock transition |+| 14 | 6D | input | Data input 6; captured into flip-flop 6 on LOW-to-HIGH clock transition |+| 15 | 6Q | tri_state | Tristate output 6; set to D6 input level on positive clock edge when OE is LOW |+| 16 | 7Q | tri_state | Tristate output 7; set to D7 input level on positive clock edge when OE is LOW |+| 17 | 7D | input | Data input 7; captured into flip-flop 7 on LOW-to-HIGH clock transition |+| 18 | 8D | input | Data input 8; captured into flip-flop 8 on LOW-to-HIGH clock transition |+| 19 | 8Q | tri_state | Tristate output 8; set to D8 input level on positive clock edge when OE is LOW |+| 20 | VCC | power_in | Supply voltage input; 4.5V to 5.5V for ACT series devices |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `CD74ACT374M96`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `cd74act374m96-etched.step` / `cd74act374m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74act374m96.step` / `cd74act374m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74ac374) (26 pp, sha256 `9c177479ef16b7a3`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74act374m96-datasheet.pdf)
page.jsonadded+228@@ -0,0 +1,228 @@+{+ "slug": "cd74act374m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74act374m96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74act374m96.kicad_sym",+ "cd74act374m96.kicad_mod",+ "cd74act374m96.glb",+ "cd74act374m96.step",+ "cd74act374m96.lbr",+ "docs/hero.png",+ "docs/cd74act374m96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD74ACT374M96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20-300mil",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74ac374",+ "parts": {+ "symbol": "cd74act374m96.kicad_sym",+ "footprint": "cd74act374m96.kicad_mod",+ "model_3d": "cd74act374m96-etched.glb",+ "model_3d_plain": "cd74act374m96.glb",+ "model_3d_step": "cd74act374m96-etched.step",+ "model_3d_step_plain": "cd74act374m96.step",+ "lbr": "cd74act374m96.lbr"+ },+ "distributor_links": {+ "lcsc": "C2869560",+ "digikey": "296-14500-2-ND",+ "mouser": "595-CD74ACT374M96"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T00:43:20Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-14500-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74ACT374M96",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Output enable input; places Q outputs in high-impedance state when HIGH"+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "tri_state",+ "description": "Tristate output 1; set to D1 input level on positive clock edge when OE is LOW"+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "Data input 1; captured into flip-flop 1 on LOW-to-HIGH clock transition"+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "Data input 2; captured into flip-flop 2 on LOW-to-HIGH clock transition"+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "tri_state",+ "description": "Tristate output 2; set to D2 input level on positive clock edge when OE is LOW"+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "tri_state",+ "description": "Tristate output 3; set to D3 input level on positive clock edge when OE is LOW"+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "Data input 3; captured into flip-flop 3 on LOW-to-HIGH clock transition"+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "Data input 4; captured into flip-flop 4 on LOW-to-HIGH clock transition"+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "tri_state",+ "description": "Tristate output 4; set to D4 input level on positive clock edge when OE is LOW"+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference potential"+ },+ {+ "number": "11",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; positive transition captures data from D inputs into flip-flops"+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "tri_state",+ "description": "Tristate output 5; set to D5 input level on positive clock edge when OE is LOW"+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "Data input 5; captured into flip-flop 5 on LOW-to-HIGH clock transition"+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "Data input 6; captured into flip-flop 6 on LOW-to-HIGH clock transition"+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "tri_state",+ "description": "Tristate output 6; set to D6 input level on positive clock edge when OE is LOW"+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "tri_state",+ "description": "Tristate output 7; set to D7 input level on positive clock edge when OE is LOW"+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "Data input 7; captured into flip-flop 7 on LOW-to-HIGH clock transition"+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "Data input 8; captured into flip-flop 8 on LOW-to-HIGH clock transition"+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "tri_state",+ "description": "Tristate output 8; set to D8 input level on positive clock edge when OE is LOW"+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage input; 4.5V to 5.5V for ACT series devices"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 26,+ "cost_usd": 0.1774,+ "at": "2026-10-01T00:43:03"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74ac374",+ "pages": 26,+ "sha256": "9c177479ef16b7a3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}