CD74ACT174M96

@@ -68,43 +68,43 @@         "number": "1",         "name": "CLR",         "type": "input",-        "description": "Active-low asynchronous clear input forcing all Q outputs low; minimum pulse width 4 ns (\u221255\u00b0C to 125\u00b0C) or 3.5 ns (\u221240\u00b0C to 85\u00b0C)."+        "description": "Active-low asynchronous clear input forcing all Q outputs low; minimum pulse width 4 ns (−55°C to 125°C) or 3.5 ns (−40°C to 85°C)."       },       {         "number": "2",         "name": "1Q",         "type": "output",-        "description": "Q output of flip-flop 1; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 1; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "3",         "name": "1D",         "type": "input",-        "description": "D input of flip-flop 1 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."+        "description": "D input of flip-flop 1 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."       },       {         "number": "4",         "name": "2D",         "type": "input",-        "description": "D input of flip-flop 2 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."+        "description": "D input of flip-flop 2 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."       },       {         "number": "5",         "name": "2Q",         "type": "output",-        "description": "Q output of flip-flop 2; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 2; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "6",         "name": "3D",         "type": "input",-        "description": "D input of flip-flop 3 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."+        "description": "D input of flip-flop 3 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."       },       {         "number": "7",         "name": "3Q",         "type": "output",-        "description": "Q output of flip-flop 3; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 3; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "8",@@ -116,43 +116,43 @@         "number": "9",         "name": "CLK",         "type": "input",-        "description": "Positive-edge-triggered clock input; minimum pulse width 6.2 ns (\u221255\u00b0C to 125\u00b0C) or 5.4 ns (\u221240\u00b0C to 85\u00b0C); maximum frequency 80 MHz (\u221255\u00b0C to 125\u00b0C) or 91 MHz (\u221240\u00b0C to 85\u00b0C)."+        "description": "Positive-edge-triggered clock input; minimum pulse width 6.2 ns (−55°C to 125°C) or 5.4 ns (−40°C to 85°C); maximum frequency 80 MHz (−55°C to 125°C) or 91 MHz (−40°C to 85°C)."       },       {         "number": "10",         "name": "4Q",         "type": "output",-        "description": "Q output of flip-flop 4; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 4; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "11",         "name": "4D",         "type": "input",-        "description": "D input of flip-flop 4 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."+        "description": "D input of flip-flop 4 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."       },       {         "number": "12",         "name": "5Q",         "type": "output",-        "description": "Q output of flip-flop 5; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 5; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "13",         "name": "5D",         "type": "input",-        "description": "D input of flip-flop 5 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."+        "description": "D input of flip-flop 5 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."       },       {         "number": "14",         "name": "6D",         "type": "input",-        "description": "D input of flip-flop 6 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."+        "description": "D input of flip-flop 6 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."       },       {         "number": "15",         "name": "6Q",         "type": "output",-        "description": "Q output of flip-flop 6; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 6; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "16",@@ -193,6 +193,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "cd74act174m96.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6.0,+          9.9,+          1.75+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "cd74act174m96-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6.0,+          9.9,+          1.75+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "0686ab1ba5795b173bf7fdb298a24a6dec82d9a444a77bc198851ea3ae5b4590",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}