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CD74ACT174M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# CD74ACT174M96++**Texas Instruments** · Flip Flops · SOIC-16++CD74ACT174M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLR | input | Active-low asynchronous clear input forcing all Q outputs low; minimum pulse width 4 ns (−55°C to 125°C) or 3.5 ns (−40°C to 85°C). |+| 2 | 1Q | output | Q output of flip-flop 1; drives up to ±24 mA with output voltage range 0.1 to 4.4 V. |+| 3 | 1D | input | D input of flip-flop 1 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V. |+| 4 | 2D | input | D input of flip-flop 2 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V. |+| 5 | 2Q | output | Q output of flip-flop 2; drives up to ±24 mA with output voltage range 0.1 to 4.4 V. |+| 6 | 3D | input | D input of flip-flop 3 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V. |+| 7 | 3Q | output | Q output of flip-flop 3; drives up to ±24 mA with output voltage range 0.1 to 4.4 V. |+| 8 | GND | power_in | Ground reference pin; 0 V. |+| 9 | CLK | input | Positive-edge-triggered clock input; minimum pulse width 6.2 ns (−55°C to 125°C) or 5.4 ns (−40°C to 85°C); maximum frequency 80 MHz (−55°C to 125°C) or 91 MHz (−40°C to 85°C). |+| 10 | 4Q | output | Q output of flip-flop 4; drives up to ±24 mA with output voltage range 0.1 to 4.4 V. |+| 11 | 4D | input | D input of flip-flop 4 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V. |+| 12 | 5Q | output | Q output of flip-flop 5; drives up to ±24 mA with output voltage range 0.1 to 4.4 V. |+| 13 | 5D | input | D input of flip-flop 5 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V. |+| 14 | 6D | input | D input of flip-flop 6 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V. |+| 15 | 6Q | output | Q output of flip-flop 6; drives up to ±24 mA with output voltage range 0.1 to 4.4 V. |+| 16 | VCC | power_in | Power supply input; nominal 5 V, operating range 4.5 to 5.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74ACT174M96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74act174m96-etched.step` / `cd74act174m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74act174m96.step` / `cd74act174m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74act174) (28 pp, sha256 `104a411f36c5aecd`, retrieved 2026-09-27, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74act174m96-datasheet.pdf)
page.jsonadded+204@@ -0,0 +1,204 @@+{+ "slug": "cd74act174m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74act174m96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74act174m96.kicad_sym",+ "cd74act174m96.kicad_mod",+ "cd74act174m96.glb",+ "cd74act174m96.step",+ "cd74act174m96.lbr",+ "docs/hero.png",+ "docs/cd74act174m96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD74ACT174M96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74act174",+ "parts": {+ "symbol": "cd74act174m96.kicad_sym",+ "footprint": "cd74act174m96.kicad_mod",+ "model_3d": "cd74act174m96-etched.glb",+ "model_3d_plain": "cd74act174m96.glb",+ "model_3d_step": "cd74act174m96-etched.step",+ "model_3d_step_plain": "cd74act174m96.step",+ "lbr": "cd74act174m96.lbr"+ },+ "distributor_links": {+ "lcsc": "C2869384",+ "digikey": "2156-CD74ACT174M96-HCTR-ND",+ "mouser": "595-CD74ACT174M96"+ },+ "distributor_check": {+ "checked_at": "2026-09-27T06:44:37Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-CD74ACT174M96-HCTR-ND",+ "status": "found",+ "lifecycle": "Obsolete"+ },+ "mouser": {+ "pn": "595-CD74ACT174M96",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CLR",+ "type": "input",+ "description": "Active-low asynchronous clear input forcing all Q outputs low; minimum pulse width 4 ns (−55°C to 125°C) or 3.5 ns (−40°C to 85°C)."+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "output",+ "description": "Q output of flip-flop 1; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "D input of flip-flop 1 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "D input of flip-flop 2 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "output",+ "description": "Q output of flip-flop 2; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+ },+ {+ "number": "6",+ "name": "3D",+ "type": "input",+ "description": "D input of flip-flop 3 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+ },+ {+ "number": "7",+ "name": "3Q",+ "type": "output",+ "description": "Q output of flip-flop 3; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference pin; 0 V."+ },+ {+ "number": "9",+ "name": "CLK",+ "type": "input",+ "description": "Positive-edge-triggered clock input; minimum pulse width 6.2 ns (−55°C to 125°C) or 5.4 ns (−40°C to 85°C); maximum frequency 80 MHz (−55°C to 125°C) or 91 MHz (−40°C to 85°C)."+ },+ {+ "number": "10",+ "name": "4Q",+ "type": "output",+ "description": "Q output of flip-flop 4; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+ },+ {+ "number": "11",+ "name": "4D",+ "type": "input",+ "description": "D input of flip-flop 4 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "output",+ "description": "Q output of flip-flop 5; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "D input of flip-flop 5 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "D input of flip-flop 6 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "output",+ "description": "Q output of flip-flop 6; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply input; nominal 5 V, operating range 4.5 to 5.5 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 28,+ "cost_usd": 0.2462,+ "at": "2026-09-27T06:44:18"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74act174",+ "pages": 28,+ "sha256": "104a411f36c5aecd",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}