CD74ACT174M96 - Commit

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cd74act174m96: factory component page (tier=lcsc)

Ray ·740e363be6 ·1mo ago ·parent 0c8761d

3 files changed +18154−37

cd74act174m96-etched.glbcd74act174m96-etched.step+18096 page.json+58−37

cd74act174m96-etched.glbadded

⋯ 1 unchanged line ⋯

cd74act174m96-etched.stepadded+18096

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page.json+58−37

@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd74act174m96",+  "title": "CD74ACT174M96",+  "brief": "Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",@@ -10,24 +13,6 @@     "factory-2.0.0",     "extractor-text"   ],-  "dependencies": {},-  "hero": {-    "type": "image",-    "path": "docs/hero.png"-  },-  "files": [-    "page.json",-    "README.md",-    "cd74act174m96.kicad_sym",-    "cd74act174m96.kicad_mod",-    "cd74act174m96.glb",-    "cd74act174m96.step",-    "cd74act174m96.lbr",-    "docs/hero.png",-    "docs/cd74act174m96-datasheet.pdf",-    "viewers/symbol.html",-    "viewers/footprint.html"-  ],   "component": {     "mpn": "CD74ACT174M96",     "manufacturer": "Texas Instruments",@@ -68,43 +53,43 @@         "number": "1",         "name": "CLR",         "type": "input",-        "description": "Active-low asynchronous clear input forcing all Q outputs low; minimum pulse width 4 ns (−55°C to 125°C) or 3.5 ns (−40°C to 85°C)."+        "description": "Active-low asynchronous clear input forcing all Q outputs low; minimum pulse width 4 ns (\u221255\u00b0C to 125\u00b0C) or 3.5 ns (\u221240\u00b0C to 85\u00b0C)."       },       {         "number": "2",         "name": "1Q",         "type": "output",-        "description": "Q output of flip-flop 1; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 1; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "3",         "name": "1D",         "type": "input",-        "description": "D input of flip-flop 1 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+        "description": "D input of flip-flop 1 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."       },       {         "number": "4",         "name": "2D",         "type": "input",-        "description": "D input of flip-flop 2 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+        "description": "D input of flip-flop 2 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."       },       {         "number": "5",         "name": "2Q",         "type": "output",-        "description": "Q output of flip-flop 2; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 2; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "6",         "name": "3D",         "type": "input",-        "description": "D input of flip-flop 3 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+        "description": "D input of flip-flop 3 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."       },       {         "number": "7",         "name": "3Q",         "type": "output",-        "description": "Q output of flip-flop 3; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 3; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "8",@@ -116,43 +101,43 @@         "number": "9",         "name": "CLK",         "type": "input",-        "description": "Positive-edge-triggered clock input; minimum pulse width 6.2 ns (−55°C to 125°C) or 5.4 ns (−40°C to 85°C); maximum frequency 80 MHz (−55°C to 125°C) or 91 MHz (−40°C to 85°C)."+        "description": "Positive-edge-triggered clock input; minimum pulse width 6.2 ns (\u221255\u00b0C to 125\u00b0C) or 5.4 ns (\u221240\u00b0C to 85\u00b0C); maximum frequency 80 MHz (\u221255\u00b0C to 125\u00b0C) or 91 MHz (\u221240\u00b0C to 85\u00b0C)."       },       {         "number": "10",         "name": "4Q",         "type": "output",-        "description": "Q output of flip-flop 4; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 4; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "11",         "name": "4D",         "type": "input",-        "description": "D input of flip-flop 4 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+        "description": "D input of flip-flop 4 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."       },       {         "number": "12",         "name": "5Q",         "type": "output",-        "description": "Q output of flip-flop 5; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 5; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "13",         "name": "5D",         "type": "input",-        "description": "D input of flip-flop 5 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+        "description": "D input of flip-flop 5 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."       },       {         "number": "14",         "name": "6D",         "type": "input",-        "description": "D input of flip-flop 6 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V."+        "description": "D input of flip-flop 6 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (\u221255\u00b0C to 125\u00b0C) or 2.2 ns (\u221240\u00b0C to 85\u00b0C); requires VIH \u2265 2 V or VIL \u2264 0.8 V."       },       {         "number": "15",         "name": "6Q",         "type": "output",-        "description": "Q output of flip-flop 6; drives up to ±24 mA with output voltage range 0.1 to 4.4 V."+        "description": "Q output of flip-flop 6; drives up to \u00b124 mA with output voltage range 0.1 to 4.4 V."       },       {         "number": "16",@@ -195,10 +180,46 @@       "footprint": "viewers/footprint.html"     }   },-  "visibility": "public",-  "org": "adom",+  "metadata": {+    "specs": {+      "Manufacturer": "Texas Instruments",+      "Package": "SOIC-16",+      "Category": "Logic",+      "Pins": "16"+    }+  },+  "variants": [],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd74act174m96"+  ],+  "discovery_pitch": "CD74ACT174M96 (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",   "author": {     "name": "Ray",     "email": "[email protected]"-  }+  },+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd74act174m96.kicad_sym",+    "cd74act174m96.kicad_mod",+    "cd74act174m96.glb",+    "cd74act174m96.step",+    "cd74act174m96.lbr",+    "docs/hero.png",+    "docs/cd74act174m96-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ] }\ No newline at end of file