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CD74AC10M96
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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# CD74AC10M96++**Texas Instruments** · Logic Gates · SOIC-14++CD74AC10M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Input A of NAND gate 1; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 2 | 1B | input | Input B of NAND gate 1; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 3 | 2A | input | Input A of NAND gate 2; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 4 | 2B | input | Input B of NAND gate 2; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 5 | 2C | input | Input C of NAND gate 2; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 6 | 2Y | output | Output Y of NAND gate 2; rated for ±24 mA drive (IOH −24 mA and IOL 24 mA at VCC 4.5 V to 5.5 V). |+| 7 | GND | power_in | Ground reference for the device. |+| 8 | 3Y | output | Output Y of NAND gate 3; rated for ±24 mA drive (IOH −24 mA and IOL 24 mA at VCC 4.5 V to 5.5 V). |+| 9 | 3A | input | Input A of NAND gate 3; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 10 | 3B | input | Input B of NAND gate 3; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 11 | 3C | input | Input C of NAND gate 3; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 12 | 1Y | output | Output Y of NAND gate 1; rated for ±24 mA drive (IOH −24 mA and IOL 24 mA at VCC 4.5 V to 5.5 V). |+| 13 | 1C | input | Input C of NAND gate 1; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND. |+| 14 | VCC | power_in | Supply voltage; recommended operating range is 1.5 V to 5.5 V, with an absolute maximum of 6 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD74AC10M96`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `cd74ac10m96-etched.step` / `cd74ac10m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74ac10m96.step` / `cd74ac10m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74ac10) (14 pp, sha256 `067c1f29684ac2d2`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74ac10m96-datasheet.pdf)
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input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Input B of NAND gate 1; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "3",+ "name": "2A",+ "type": "input",+ "description": "Input A of NAND gate 2; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "4",+ "name": "2B",+ "type": "input",+ "description": "Input B of NAND gate 2; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "5",+ "name": "2C",+ "type": "input",+ "description": "Input C of NAND gate 2; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Output Y of NAND gate 2; rated for ±24 mA drive (IOH −24 mA and IOL 24 mA at VCC 4.5 V to 5.5 V)."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Output Y of NAND gate 3; rated for ±24 mA drive (IOH −24 mA and IOL 24 mA at VCC 4.5 V to 5.5 V)."+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Input A of NAND gate 3; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Input B of NAND gate 3; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "11",+ "name": "3C",+ "type": "input",+ "description": "Input C of NAND gate 3; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "12",+ "name": "1Y",+ "type": "output",+ "description": "Output Y of NAND gate 1; rated for ±24 mA drive (IOH −24 mA and IOL 24 mA at VCC 4.5 V to 5.5 V)."+ },+ {+ "number": "13",+ "name": "1C",+ "type": "input",+ "description": "Input C of NAND gate 1; input voltage must stay between 0 V and VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; 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