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CD4099BM96
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Texas Instruments Latches, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4099BM96++**Texas Instruments** · Latches · SOIC-16++CD4099BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q7 | output | Active parallel latch output for bit 7; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions. |+| 2 | RESET | input | Master reset input; when RESET and WRITE DISABLE are both high all 8 latch bits are reset to a logic 0 level. |+| 3 | DATA | input | Serial data input written into the latch addressed by A0-A2 when WRITE DISABLE is low; input voltage range is -0.5V to VDD+0.5V. |+| 4 | WRITE DISABLE | input | Control input (WD); when low, data entry to the addressed latch is enabled, and when high data entry is inhibited while all outputs can still be read (see Mode Selection table). |+| 5 | A0 | input | Address input (least significant) used with A1 and A2 to select which of the 8 latch bits is written to or, in demultiplexer mode, which output is active. |+| 6 | A1 | input | Address input used with A0 and A2 to select which of the 8 latch bits is written to or, in demultiplexer mode, which output is active. |+| 7 | A2 | input | Address input (most significant) used with A0 and A1 to select which of the 8 latch bits is written to or, in demultiplexer mode, which output is active. |+| 8 | VSS | power_in | Negative supply/ground reference terminal for the device (0V reference for VDD and input voltage ranges). |+| 9 | Q0 | output | Active parallel latch output for bit 0; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions. |+| 10 | Q1 | output | Active parallel latch output for bit 1; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions. |+| 11 | Q2 | output | Active parallel latch output for bit 2; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions. |+| 12 | Q3 | output | Active parallel latch output for bit 3; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions. |+| 13 | Q4 | output | Active parallel latch output for bit 4; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions. |+| 14 | Q5 | output | Active parallel latch output for bit 5; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions. |+| 15 | Q6 | output | Active parallel latch output for bit 6; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions. |+| 16 | VDD | power_in | Positive supply voltage terminal; DC supply-voltage range is -0.5V to +20V referenced to VSS, with a recommended operating supply range of 3V to 18V over the full package temperature range. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4099BM96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd4099bm96-etched.step` / `cd4099bm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4099bm96.step` / `cd4099bm96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4099b) (19 pp, sha256 `52fc48c47f5273e0`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4099bm96-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "cd4099bm96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Latches, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4099bm96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4099bm96.kicad_sym",+ "cd4099bm96.kicad_mod",+ "cd4099bm96.glb",+ "cd4099bm96.step",+ "cd4099bm96.lbr",+ "docs/hero.png",+ "docs/cd4099bm96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4099BM96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd4099b",+ "parts": {+ "symbol": "cd4099bm96.kicad_sym",+ "footprint": "cd4099bm96.kicad_mod",+ "model_3d": "cd4099bm96-etched.glb",+ "model_3d_plain": "cd4099bm96.glb",+ "model_3d_step": "cd4099bm96-etched.step",+ "model_3d_step_plain": "cd4099bm96.step",+ "lbr": "cd4099bm96.lbr"+ },+ "distributor_links": {+ "lcsc": "C131942"+ },+ "pins": [+ {+ "number": "1",+ "name": "Q7",+ "type": "output",+ "description": "Active parallel latch output for bit 7; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions."+ },+ {+ "number": "2",+ "name": "RESET",+ "type": "input",+ "description": "Master reset input; when RESET and WRITE DISABLE are both high all 8 latch bits are reset to a logic 0 level."+ },+ {+ "number": "3",+ "name": "DATA",+ "type": "input",+ "description": "Serial data input written into the latch addressed by A0-A2 when WRITE DISABLE is low; input voltage range is -0.5V to VDD+0.5V."+ },+ {+ "number": "4",+ "name": "WRITE DISABLE",+ "type": "input",+ "description": "Control input (WD); when low, data entry to the addressed latch is enabled, and when high data entry is inhibited while all outputs can still be read (see Mode Selection table)."+ },+ {+ "number": "5",+ "name": "A0",+ "type": "input",+ "description": "Address input (least significant) used with A1 and A2 to select which of the 8 latch bits is written to or, in demultiplexer mode, which output is active."+ },+ {+ "number": "6",+ "name": "A1",+ "type": "input",+ "description": "Address input used with A0 and A2 to select which of the 8 latch bits is written to or, in demultiplexer mode, which output is active."+ },+ {+ "number": "7",+ "name": "A2",+ "type": "input",+ "description": "Address input (most significant) used with A0 and A1 to select which of the 8 latch bits is written to or, in demultiplexer mode, which output is active."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply/ground reference terminal for the device (0V reference for VDD and input voltage ranges)."+ },+ {+ "number": "9",+ "name": "Q0",+ "type": "output",+ "description": "Active parallel latch output for bit 0; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions."+ },+ {+ "number": "10",+ "name": "Q1",+ "type": "output",+ "description": "Active parallel latch output for bit 1; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions."+ },+ {+ "number": "11",+ "name": "Q2",+ "type": "output",+ "description": "Active parallel latch output for bit 2; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions."+ },+ {+ "number": "12",+ "name": "Q3",+ "type": "output",+ "description": "Active parallel latch output for bit 3; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions."+ },+ {+ "number": "13",+ "name": "Q4",+ "type": "output",+ "description": "Active parallel latch output for bit 4; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions."+ },+ {+ "number": "14",+ "name": "Q5",+ "type": "output",+ "description": "Active parallel latch output for bit 5; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions."+ },+ {+ "number": "15",+ "name": "Q6",+ "type": "output",+ "description": "Active parallel latch output for bit 6; follows DATA when addressed via A0-A2 with WRITE DISABLE low, or is reset to logic 0 by RESET/mode conditions."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage terminal; DC supply-voltage range is -0.5V to +20V referenced to VSS, with a recommended operating supply range of 3V to 18V over the full package temperature range."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 19,+ "cost_usd": 0.5497,+ "at": "2026-09-23T20:46:07"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd4099b",+ "pages": 19,+ "sha256": "52fc48c47f5273e0",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}