CD4094B

@@ -0,0 +1,60 @@+# CD4094B++**Texas Instruments** · 8-stage shift-and-store register · SOIC-16++An 8-stage serial-in, parallel-out shift register with a separate output latch, in SOIC-16, the 4000-series counterpart of the 74HC595. Data clocked in on DATA/CLOCK shifts through eight stages; a STROBE pin then transfers the shifted value into eight latches so the parallel outputs (Q1-Q8) update all at once and stay steady while the next byte shifts in. The 3-state outputs and two serial outputs (QS, Q'S) let you cascade several to drive long strings of LEDs, relays, or display digits from three microcontroller pins. Runs 3-18 V.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | STROBE | input | Storage-register strobe input. When held high, data in the shift register is transferred to the 8-bit storage latch and appears on Q1-Q8 (subject to OUTPUT ENABLE). Held low, the storage latch retains its previous state. |+| 2 | DATA | input | Serial data input. Sampled into stage 1 of the shift register on each positive edge of CLOCK. |+| 3 | CLOCK | input | Clock input for the 8-stage serial shift register. Data on the DATA input is shifted into the register on the positive-going edge. Minimum clock pulse width tW=100 ns typ at VDD=10 V; fCL max=2.5 MHz at VDD=10 V. |+| 4 | Q1 | tri_state | 3-state parallel output for shift-register stage 1 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low. |+| 5 | Q2 | tri_state | 3-state parallel output for shift-register stage 2 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low. |+| 6 | Q3 | tri_state | 3-state parallel output for shift-register stage 3 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low. |+| 7 | Q4 | tri_state | 3-state parallel output for shift-register stage 4 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low. |+| 8 | VSS | power_in | Negative supply / ground reference. Tie to 0 V. |+| 9 | Q'S | output | Serial cascade output taken from the shift-register stage 8 on the NEXT NEGATIVE clock edge. Used to cascade a following CD4094B when the clock rise time is slow (allows the receiving device more setup time). |+| 10 | QS | output | Serial cascade output taken from shift-register stage 8 on the POSITIVE clock edge. Used to cascade a following CD4094B for high-speed operation when the clock rise time is fast. |+| 11 | Q8 | tri_state | 3-state parallel output for shift-register stage 8 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low. |+| 12 | Q7 | tri_state | 3-state parallel output for shift-register stage 7 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low. |+| 13 | Q6 | tri_state | 3-state parallel output for shift-register stage 6 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low. |+| 14 | Q5 | tri_state | 3-state parallel output for shift-register stage 5 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low. |+| 15 | OUTPUT_ENABLE | input | Output-enable input for the 3-state parallel outputs Q1-Q8. High = outputs driven (enabled); Low = outputs high-impedance (open circuit). Allows Q1-Q8 to be tied directly to a common bus. |+| 16 | VDD | power_in | Positive supply. Operating range VDD-VSS = 3 V to 18 V (absolute max -0.5 V to +20 V). Bypass with a local decoupling capacitor. |++## Key specifications++| Parameter | Value |+|---|---|+| Type | 8-stage shift-and-store register |+| Data path | serial in, parallel out (Q1-Q8) |+| Latch | STROBE transfers shift to output |+| Outputs | 3-state + serial (QS, Q'S) |+| Cascade | yes (QS to next DATA) |+| Logic family | 4000B CMOS |+| Supply voltage | 3-18 V |+| Package | SOIC-16 |++## Ordering variants++- `CD4094BM (SOIC-16, tube)`+- `CD4094BM96 (SOIC-16, tape & reel)`++## CAD (KiCad official)++- Symbol: `CD4094B (generated from datasheet; KiCad has no symbol)`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4094b.pdf) (18 pp, sha256 `e64a88bc0597c967`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4094b-datasheet.pdf)

@@ -0,0 +1,36 @@+{+  "slug": "cd4094b",+  "version": "0.1.0",+  "type": "component",+  "description": "TI 8-stage serial shift register with output latch and 3-state outputs, SOIC-16. Like a CMOS 74HC595. 3-18 V. Datasheet-verified.",+  "tags": [+    "component",+    "logic",+    "shift-register",+    "serial-to-parallel",+    "4094",+    "soic-16",+    "texas-instruments"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4094b.kicad_sym",+    "cd4094b.kicad_mod",+    "cd4094b.glb",+    "docs/hero.png",+    "docs/cd4094b-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file