CD4094B

@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4094b",+  "title": "CD4094B",+  "brief": "TI 8-stage serial shift register with output latch and 3-state outputs, SOIC-16. Like a CMOS 74HC595. 3-18 V. Datasheet-verified.",   "version": "0.1.0",-  "type": "component",-  "description": "TI 8-stage serial shift register with output latch and 3-state outputs, SOIC-16. Like a CMOS 74HC595. 3-18 V. Datasheet-verified.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",@@ -12,6 +15,170 @@     "soic-16",     "texas-instruments"   ],+  "component": {+    "mpn": "CD4094B",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-16",+    "pin_count": 16,+    "category": "Logic IC",+    "subcategory": "8-stage shift-and-store register",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4094b.pdf",+    "parts": {+      "symbol": "cd4094b.kicad_sym",+      "footprint": "cd4094b.kicad_mod",+      "model_3d": "cd4094b.glb"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "STROBE",+        "type": "input",+        "description": "Storage-register strobe input. When held high, data in the shift register is transferred to the 8-bit storage latch and appears on Q1-Q8 (subject to OUTPUT ENABLE). Held low, the storage latch retains its previous state."+      },+      {+        "number": "2",+        "name": "DATA",+        "type": "input",+        "description": "Serial data input. Sampled into stage 1 of the shift register on each positive edge of CLOCK."+      },+      {+        "number": "3",+        "name": "CLOCK",+        "type": "input",+        "description": "Clock input for the 8-stage serial shift register. Data on the DATA input is shifted into the register on the positive-going edge. Minimum clock pulse width tW=100 ns typ at VDD=10 V; fCL max=2.5 MHz at VDD=10 V."+      },+      {+        "number": "4",+        "name": "Q1",+        "type": "tri_state",+        "description": "3-state parallel output for shift-register stage 1 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low."+      },+      {+        "number": "5",+        "name": "Q2",+        "type": "tri_state",+        "description": "3-state parallel output for shift-register stage 2 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low."+      },+      {+        "number": "6",+        "name": "Q3",+        "type": "tri_state",+        "description": "3-state parallel output for shift-register stage 3 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low."+      },+      {+        "number": "7",+        "name": "Q4",+        "type": "tri_state",+        "description": "3-state parallel output for shift-register stage 4 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low."+      },+      {+        "number": "8",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference. Tie to 0 V."+      },+      {+        "number": "9",+        "name": "Q'S",+        "type": "output",+        "description": "Serial cascade output taken from the shift-register stage 8 on the NEXT NEGATIVE clock edge. Used to cascade a following CD4094B when the clock rise time is slow (allows the receiving device more setup time)."+      },+      {+        "number": "10",+        "name": "QS",+        "type": "output",+        "description": "Serial cascade output taken from shift-register stage 8 on the POSITIVE clock edge. Used to cascade a following CD4094B for high-speed operation when the clock rise time is fast."+      },+      {+        "number": "11",+        "name": "Q8",+        "type": "tri_state",+        "description": "3-state parallel output for shift-register stage 8 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low."+      },+      {+        "number": "12",+        "name": "Q7",+        "type": "tri_state",+        "description": "3-state parallel output for shift-register stage 7 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low."+      },+      {+        "number": "13",+        "name": "Q6",+        "type": "tri_state",+        "description": "3-state parallel output for shift-register stage 6 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low."+      },+      {+        "number": "14",+        "name": "Q5",+        "type": "tri_state",+        "description": "3-state parallel output for shift-register stage 5 (via the storage latch). Enabled when OUTPUT ENABLE is high; open-circuit when OUTPUT ENABLE is low."+      },+      {+        "number": "15",+        "name": "OUTPUT_ENABLE",+        "type": "input",+        "description": "Output-enable input for the 3-state parallel outputs Q1-Q8. High = outputs driven (enabled); Low = outputs high-impedance (open circuit). Allows Q1-Q8 to be tied directly to a common bus."+      },+      {+        "number": "16",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply. Operating range VDD-VSS = 3 V to 18 V (absolute max -0.5 V to +20 V). Bypass with a local decoupling capacitor."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/cd4094b.pdf",+        "pages": 18,+        "sha256": "e64a88bc0597c967",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Type": "8-stage shift-and-store register",+      "Data path": "serial in, parallel out (Q1-Q8)",+      "Latch": "STROBE transfers shift to output",+      "Outputs": "3-state + serial (QS, Q'S)",+      "Cascade": "yes (QS to next DATA)",+      "Logic family": "4000B CMOS",+      "Supply voltage": "3-18 V",+      "Package": "SOIC-16"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd4094b",+    "cd4094",+    "shift register",+    "serial to parallel",+    "4094 latch"+  ],+  "discovery_pitch": "CD4094B 8-stage shift-and-store register (SOIC-16) with datasheet-verified pinout, KiCad footprint/3D, and full provenance.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -27,10 +194,5 @@     "docs/cd4094b-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file