component
CD4093BPWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# CD4093BPWR++**Texas Instruments** · Logic Gates · TSSOP-14++CD4093BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Schmitt-trigger input A of NAND gate 1 (J = NAND(A,B)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |+| 2 | B | input | Schmitt-trigger input B of NAND gate 1 (J = NAND(A,B)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |+| 3 | J | output | Output of Schmitt-trigger NAND gate 1, J = NAND(A,B), standardized symmetrical CMOS output stage. |+| 4 | K | output | Output of Schmitt-trigger NAND gate 2, K = NAND(C,D), standardized symmetrical CMOS output stage. |+| 5 | C | input | Schmitt-trigger input C of NAND gate 2 (K = NAND(C,D)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |+| 6 | D | input | Schmitt-trigger input D of NAND gate 2 (K = NAND(C,D)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |+| 7 | VSS | power_in | Negative supply / ground reference terminal; all other voltages, including VDD (−0.5 V to +20 V), are referenced to this pin. |+| 8 | E | input | Schmitt-trigger input E of NAND gate 3 (L = NAND(E,F)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |+| 9 | F | input | Schmitt-trigger input F of NAND gate 3 (L = NAND(E,F)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |+| 10 | L | output | Output of Schmitt-trigger NAND gate 3, L = NAND(E,F), standardized symmetrical CMOS output stage. |+| 11 | M | output | Output of Schmitt-trigger NAND gate 4, M = NAND(G,H), standardized symmetrical CMOS output stage. |+| 12 | G | input | Schmitt-trigger input G of NAND gate 4 (M = NAND(G,H)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |+| 13 | H | input | Schmitt-trigger input H of NAND gate 4 (M = NAND(G,H)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |+| 14 | VDD | power_in | Positive supply pin; DC supply-voltage range −0.5 V to +20 V referenced to VSS, recommended operating supply range 3 V to 18 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD4093BPWR`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `cd4093bpwr-etched.step` / `cd4093bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4093bpwr.step` / `cd4093bpwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4093b.pdf) (21 pp, sha256 `c981171c0409a8a0`, retrieved 2026-09-23, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4093bpwr-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4093bpwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4093bpwr.kicad_sym",+ "cd4093bpwr.kicad_mod",+ "cd4093bpwr.glb",+ "cd4093bpwr.step",+ "cd4093bpwr.lbr",+ "docs/hero.png",+ "docs/cd4093bpwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4093BPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd4093b.pdf",+ "parts": {+ "symbol": "cd4093bpwr.kicad_sym",+ "footprint": "cd4093bpwr.kicad_mod",+ "model_3d": "cd4093bpwr-etched.glb",+ "model_3d_plain": "cd4093bpwr.glb",+ "model_3d_step": "cd4093bpwr-etched.step",+ "model_3d_step_plain": "cd4093bpwr.step",+ "lbr": "cd4093bpwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C88243"+ },+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Schmitt-trigger input A of NAND gate 1 (J = NAND(A,B)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Schmitt-trigger input B of NAND gate 1 (J = NAND(A,B)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature."+ },+ {+ "number": "3",+ "name": "J",+ "type": "output",+ "description": "Output of Schmitt-trigger NAND gate 1, J = NAND(A,B), standardized symmetrical CMOS output stage."+ },+ {+ "number": "4",+ "name": "K",+ "type": "output",+ "description": "Output of Schmitt-trigger NAND gate 2, K = NAND(C,D), standardized symmetrical CMOS output stage."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Schmitt-trigger input C of NAND gate 2 (K = NAND(C,D)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Schmitt-trigger input D of NAND gate 2 (K = NAND(C,D)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground reference terminal; all other voltages, including VDD (−0.5 V to +20 V), are referenced to this pin."+ },+ {+ "number": "8",+ "name": "E",+ "type": "input",+ "description": "Schmitt-trigger input E of NAND gate 3 (L = NAND(E,F)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature."+ },+ {+ "number": "9",+ "name": "F",+ "type": "input",+ "description": "Schmitt-trigger input F of NAND gate 3 (L = NAND(E,F)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature."+ },+ {+ "number": "10",+ "name": "L",+ "type": "output",+ "description": "Output of Schmitt-trigger NAND gate 3, L = NAND(E,F), standardized symmetrical CMOS output stage."+ },+ {+ "number": "11",+ "name": "M",+ "type": "output",+ "description": "Output of Schmitt-trigger NAND gate 4, M = NAND(G,H), standardized symmetrical CMOS output stage."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Schmitt-trigger input G of NAND gate 4 (M = NAND(G,H)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature."+ },+ {+ "number": "13",+ "name": "H",+ "type": "input",+ "description": "Schmitt-trigger input H of NAND gate 4 (M = NAND(G,H)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply pin; DC supply-voltage range −0.5 V to +20 V referenced to VSS, recommended operating supply range 3 V to 18 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 21,+ "cost_usd": 0.7331,+ "at": "2026-09-23T08:46:23"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd4093b.pdf",+ "pages": 21,+ "sha256": "c981171c0409a8a0",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}