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cd4093bm96: factory component page (tier=mfr)

Ray ·6dc492c410 · ·parent 72d339e
1 file changed +152−8
page.json+152−8
@@ -1,13 +1,162 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4093bm96",+  "title": "CD4093BM96",+  "brief": "Texas Instruments Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Texas Instruments Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "cd4093bm96"   ],+  "component": {+    "mpn": "CD4093BM96",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Gates",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4093bm96.pdf",+    "parts": {+      "symbol": "cd4093bm96.kicad_sym",+      "footprint": "cd4093bm96.kicad_mod",+      "model_3d": "cd4093bm96.glb",+      "model_3d_step": "cd4093bm96.step",+      "lbr": "cd4093bm96.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "1A",+        "type": "input",+        "description": "Schmitt-trigger input A of NAND gate 1. High-impedance CMOS input protected by internal diode network; typical input current 10 pA. Hysteresis (VP-VN) ~0.9 V at VDD=5 V, ~2.3 V at VDD=10 V."+      },+      {+        "number": "2",+        "name": "1B",+        "type": "input",+        "description": "Schmitt-trigger input B of NAND gate 1. High-impedance CMOS input; unused inputs must be tied to VDD or VSS (not floated). Same hysteresis characteristics as pin 1."+      },+      {+        "number": "3",+        "name": "1J",+        "type": "output",+        "description": "NAND output of gate 1 (J = A\u00b7B, i.e. NAND of pins 1 and 2). Standardized symmetrical CMOS output; typical IOL/IOH ~1 mA at VDD=5 V, rising with supply."+      },+      {+        "number": "4",+        "name": "2K",+        "type": "output",+        "description": "NAND output of gate 2 (K = C\u00b7D, NAND of pins 5 and 6). Symmetrical CMOS push-pull output."+      },+      {+        "number": "5",+        "name": "2C",+        "type": "input",+        "description": "Schmitt-trigger input C of NAND gate 2. Same characteristics as pin 1."+      },+      {+        "number": "6",+        "name": "2D",+        "type": "input",+        "description": "Schmitt-trigger input D of NAND gate 2. Same characteristics as pin 1."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference (0 V). All logic levels and hysteresis thresholds are referenced to VSS."+      },+      {+        "number": "8",+        "name": "3E",+        "type": "input",+        "description": "Schmitt-trigger input E of NAND gate 3. Same characteristics as pin 1."+      },+      {+        "number": "9",+        "name": "3F",+        "type": "input",+        "description": "Schmitt-trigger input F of NAND gate 3. Same characteristics as pin 1."+      },+      {+        "number": "10",+        "name": "3L",+        "type": "output",+        "description": "NAND output of gate 3 (L = E\u00b7F, NAND of pins 8 and 9). Symmetrical CMOS push-pull output."+      },+      {+        "number": "11",+        "name": "4M",+        "type": "output",+        "description": "NAND output of gate 4 (M = G\u00b7H, NAND of pins 12 and 13). Symmetrical CMOS push-pull output."+      },+      {+        "number": "12",+        "name": "4G",+        "type": "input",+        "description": "Schmitt-trigger input G of NAND gate 4. Same characteristics as pin 1."+      },+      {+        "number": "13",+        "name": "4H",+        "type": "input",+        "description": "Schmitt-trigger input H of NAND gate 4. Same characteristics as pin 1."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply. Recommended operating range 3 V to 18 V (absolute max -0.5 V to +20 V referenced to VSS). Bypass with a decoupling capacitor close to the pin."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/cd4093bm96.pdf",+        "pages": 17,+        "sha256": "614c8d95c9092c8e",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "Texas Instruments",+      "Package": "SOIC-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd4093bm96"+  ],+  "discovery_pitch": "CD4093BM96 (Texas Instruments) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +174,5 @@     "docs/cd4093bm96-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file