← Commit history

Set visibility: public

Ray ·3887f1ed02 · ·parent e938cc2
1 file changed +8−5
page.json+8−5
@@ -44,13 +44,13 @@         "number": "3",         "name": "1J",         "type": "output",-        "description": "NAND output of gate 1 (J = A\u00b7B, i.e. NAND of pins 1 and 2). Standardized symmetrical CMOS output; typical IOL/IOH ~1 mA at VDD=5 V, rising with supply."+        "description": "NAND output of gate 1 (J = A·B, i.e. NAND of pins 1 and 2). Standardized symmetrical CMOS output; typical IOL/IOH ~1 mA at VDD=5 V, rising with supply."       },       {         "number": "4",         "name": "2K",         "type": "output",-        "description": "NAND output of gate 2 (K = C\u00b7D, NAND of pins 5 and 6). Symmetrical CMOS push-pull output."+        "description": "NAND output of gate 2 (K = C·D, NAND of pins 5 and 6). Symmetrical CMOS push-pull output."       },       {         "number": "5",@@ -86,13 +86,13 @@         "number": "10",         "name": "3L",         "type": "output",-        "description": "NAND output of gate 3 (L = E\u00b7F, NAND of pins 8 and 9). Symmetrical CMOS push-pull output."+        "description": "NAND output of gate 3 (L = E·F, NAND of pins 8 and 9). Symmetrical CMOS push-pull output."       },       {         "number": "11",         "name": "4M",         "type": "output",-        "description": "NAND output of gate 4 (M = G\u00b7H, NAND of pins 12 and 13). Symmetrical CMOS push-pull output."+        "description": "NAND output of gate 4 (M = G·H, NAND of pins 12 and 13). Symmetrical CMOS push-pull output."       },       {         "number": "12",@@ -174,5 +174,8 @@     "docs/cd4093bm96-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file