component
CD4093BM
Public Made by Adomby adom
JSMSEMI Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.md+14@@ -43,6 +43,20 @@ CD4093BM from JSMSEMI, in a SOP-14. Pinout and pin descriptions extracted from t - Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm` - 3D model: SOP-14 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`cd4093bm.step`](cd4093bm.step) | 195 KB | You want the bare part, or you mark your own boards. |+| [`cd4093bm-etched.step`](cd4093bm-etched.step) | 2.3 MB | You want the part with `CD4093BM` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 566 faces against 237 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "cd4093bm",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "JSMSEMI Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+10−10@@ -4,7 +4,7 @@ "slug": "cd4093bm", "title": "CD4093BM", "brief": "JSMSEMI Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -46,13 +46,13 @@ "number": "3", "name": "J", "type": "output",- "description": "Gate 1 NAND output (J = NOT(A\u00b7B)). CMOS push-pull output, IOH ~ -1.8 mA at VDD=5 V; IOL ~ 3.6 mA at VDD=5 V."+ "description": "Gate 1 NAND output (J = NOT(A·B)). CMOS push-pull output, IOH ~ -1.8 mA at VDD=5 V; IOL ~ 3.6 mA at VDD=5 V." }, { "number": "4", "name": "K", "type": "output",- "description": "Gate 2 NAND output (K = NOT(C\u00b7D)). CMOS push-pull output driven by Schmitt-trigger inputs C and D."+ "description": "Gate 2 NAND output (K = NOT(C·D)). CMOS push-pull output driven by Schmitt-trigger inputs C and D." }, { "number": "5",@@ -88,13 +88,13 @@ "number": "10", "name": "L", "type": "output",- "description": "Gate 3 NAND output (L = NOT(E\u00b7F)). CMOS push-pull output driven by Schmitt-trigger inputs E and F."+ "description": "Gate 3 NAND output (L = NOT(E·F)). CMOS push-pull output driven by Schmitt-trigger inputs E and F." }, { "number": "11", "name": "M", "type": "output",- "description": "Gate 4 NAND output (M = NOT(G\u00b7H)). CMOS push-pull output driven by Schmitt-trigger inputs G and H."+ "description": "Gate 4 NAND output (M = NOT(G·H)). CMOS push-pull output driven by Schmitt-trigger inputs G and H." }, { "number": "12",@@ -112,7 +112,7 @@ "number": "14", "name": "VDD", "type": "power_in",- "description": "Positive supply. Recommended operating range 3.0 V to 15 V; absolute maximum 20 V (spec limit 18 V). Input leakage IIN \u2264 1.2 \u00b5A and quiescent IDD \u2264 1.2 \u00b5A at VDD=18 V, Ta=25 \u00b0C."+ "description": "Positive supply. Recommended operating range 3.0 V to 15 V; absolute maximum 20 V (spec limit 18 V). Input leakage IIN ≤ 1.2 µA and quiescent IDD ≤ 1.2 µA at VDD=18 V, Ta=25 °C." } ], "provenance": {@@ -186,9 +186,9 @@ "docs/hero.png", "docs/cd4093bm-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "JSMSEMI Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D." }