CD4093BM

@@ -0,0 +1,55 @@+# CD4093BM++**JSMSEMI** · Gates · SOP-14++CD4093BM from JSMSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Gate 1 input A. Schmitt-trigger input of the first 2-input NAND gate. Typical VP=3.2 V and VN=1.8 V at VDD=5 V (hysteresis ~1.4 V). |+| 2 | B | input | Gate 1 input B. Schmitt-trigger input of the first 2-input NAND gate. NAND output J = NOT(A AND B). |+| 3 | J | output | Gate 1 NAND output (J = NOT(A·B)). CMOS push-pull output, IOH ~ -1.8 mA at VDD=5 V; IOL ~ 3.6 mA at VDD=5 V. |+| 4 | K | output | Gate 2 NAND output (K = NOT(C·D)). CMOS push-pull output driven by Schmitt-trigger inputs C and D. |+| 5 | C | input | Gate 2 input C. Schmitt-trigger input of the second 2-input NAND gate; pairs with input D to drive output K. |+| 6 | D | input | Gate 2 input D. Schmitt-trigger input of the second 2-input NAND gate; pairs with input C to drive output K. |+| 7 | VSS | power_in | Negative supply / ground reference (0 V). Absolute maximum VDD-VSS is 20 V; recommended operating range 3.0 V to 15 V (up to 18 V absolute max). |+| 8 | E | input | Gate 3 input E. Schmitt-trigger input of the third 2-input NAND gate; pairs with input F to drive output L. |+| 9 | F | input | Gate 3 input F. Schmitt-trigger input of the third 2-input NAND gate; pairs with input E to drive output L. |+| 10 | L | output | Gate 3 NAND output (L = NOT(E·F)). CMOS push-pull output driven by Schmitt-trigger inputs E and F. |+| 11 | M | output | Gate 4 NAND output (M = NOT(G·H)). CMOS push-pull output driven by Schmitt-trigger inputs G and H. |+| 12 | G | input | Gate 4 input G. Schmitt-trigger input of the fourth 2-input NAND gate; pairs with input H to drive output M. |+| 13 | H | input | Gate 4 input H. Schmitt-trigger input of the fourth 2-input NAND gate; pairs with input G to drive output M. |+| 14 | VDD | power_in | Positive supply. Recommended operating range 3.0 V to 15 V; absolute maximum 20 V (spec limit 18 V). Input leakage IIN ≤ 1.2 µA and quiescent IDD ≤ 1.2 µA at VDD=18 V, Ta=25 °C. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | JSMSEMI |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `CD4093BM/TR`+- `CD4093BMCD4093BE`++## CAD (KiCad official)++- Symbol: `CD4093BM`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [JSMSEMI datasheet](docs/cd4093bm-datasheet.pdf) (5 pp, sha256 `cc5896d280d3cc68`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4093bm-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "cd4093bm",+  "version": "0.1.0",+  "type": "component",+  "description": "JSMSEMI Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "cd4093bm"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4093bm.kicad_sym",+    "cd4093bm.kicad_mod",+    "cd4093bm.glb",+    "cd4093bm.step",+    "cd4093bm.lbr",+    "docs/hero.png",+    "docs/cd4093bm-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file