component
CD4093BM
Public Made by Adomby adom
JSMSEMI Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C5456626). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+28−8
cd4093bm.lbr+20−2@@ -68,6 +68,18 @@ <smd name="12" x="2.4750" y="1.2700" dx="1.9500" dy="0.6000" layer="1"/> <smd name="13" x="2.4750" y="2.5400" dx="1.9500" dy="0.6000" layer="1"/> <smd name="14" x="2.4750" y="3.8100" dx="1.9500" dy="0.6000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-2.6000" y="4.3700"/>+ <vertex x="-2.8400" y="4.7000"/>+ <vertex x="-2.3600" y="4.7000"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.9750" y="4.3250"/>+ <vertex x="1.9500" y="4.3250"/>+ <vertex x="1.9500" y="-4.3250"/>+ <vertex x="-1.9500" y="-4.3250"/>+ <vertex x="-1.9500" y="3.3500"/>+ </polygon> <wire x1="-2.0600" y1="4.4350" x2="2.0600" y2="4.4350" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="4.3700" x2="-2.0600" y2="4.4350" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="-4.4350" x2="-2.0600" y2="-4.3700" width="0.1200" layer="21"/>@@ -76,7 +88,7 @@ <wire x1="2.0600" y1="-4.4350" x2="-2.0600" y2="-4.4350" width="0.1200" layer="21"/> <text x="0" y="5.385" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-5.385" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="4.3700"/><vertex x="-2.8400" y="4.7000"/><vertex x="-2.3600" y="4.7000"/></polygon></package>+</package> </packages> <symbols> <symbol name="CD4093BM">@@ -126,7 +138,13 @@ <connect gate="G$1" pin="F" pad="9"/> <connect gate="G$1" pin="E" pad="8"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="CD4093BM" constant="no"/>+ <attribute name="MANUFACTURER" value="JSMSEMI" constant="no"/>+ <attribute name="LCSC_PN" value="C5456626" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+8−6@@ -26,7 +26,9 @@ "model_3d_step": "cd4093bm.step", "lbr": "cd4093bm.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C5456626"+ }, "pins": [ { "number": "1",@@ -44,13 +46,13 @@ "number": "3", "name": "J", "type": "output",- "description": "Gate 1 NAND output (J = NOT(A·B)). CMOS push-pull output, IOH ~ -1.8 mA at VDD=5 V; IOL ~ 3.6 mA at VDD=5 V."+ "description": "Gate 1 NAND output (J = NOT(A\u00b7B)). CMOS push-pull output, IOH ~ -1.8 mA at VDD=5 V; IOL ~ 3.6 mA at VDD=5 V." }, { "number": "4", "name": "K", "type": "output",- "description": "Gate 2 NAND output (K = NOT(C·D)). CMOS push-pull output driven by Schmitt-trigger inputs C and D."+ "description": "Gate 2 NAND output (K = NOT(C\u00b7D)). CMOS push-pull output driven by Schmitt-trigger inputs C and D." }, { "number": "5",@@ -86,13 +88,13 @@ "number": "10", "name": "L", "type": "output",- "description": "Gate 3 NAND output (L = NOT(E·F)). CMOS push-pull output driven by Schmitt-trigger inputs E and F."+ "description": "Gate 3 NAND output (L = NOT(E\u00b7F)). CMOS push-pull output driven by Schmitt-trigger inputs E and F." }, { "number": "11", "name": "M", "type": "output",- "description": "Gate 4 NAND output (M = NOT(G·H)). CMOS push-pull output driven by Schmitt-trigger inputs G and H."+ "description": "Gate 4 NAND output (M = NOT(G\u00b7H)). CMOS push-pull output driven by Schmitt-trigger inputs G and H." }, { "number": "12",@@ -110,7 +112,7 @@ "number": "14", "name": "VDD", "type": "power_in",- "description": "Positive supply. Recommended operating range 3.0 V to 15 V; absolute maximum 20 V (spec limit 18 V). Input leakage IIN ≤ 1.2 µA and quiescent IDD ≤ 1.2 µA at VDD=18 V, Ta=25 °C."+ "description": "Positive supply. Recommended operating range 3.0 V to 15 V; absolute maximum 20 V (spec limit 18 V). Input leakage IIN \u2264 1.2 \u00b5A and quiescent IDD \u2264 1.2 \u00b5A at VDD=18 V, Ta=25 \u00b0C." } ], "provenance": {