component
CD4093BM
Public Made by Adomby adom
JSMSEMI Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+152−8@@ -1,13 +1,162 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4093bm",+ "title": "CD4093BM",+ "brief": "JSMSEMI Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "JSMSEMI Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "cd4093bm" ],+ "component": {+ "mpn": "CD4093BM",+ "manufacturer": "JSMSEMI",+ "package": "SOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2309211039_JSMSEMI-CD4093BM_C5456626.pdf",+ "parts": {+ "symbol": "cd4093bm.kicad_sym",+ "footprint": "cd4093bm.kicad_mod",+ "model_3d": "cd4093bm.glb",+ "model_3d_step": "cd4093bm.step",+ "lbr": "cd4093bm.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Gate 1 input A. Schmitt-trigger input of the first 2-input NAND gate. Typical VP=3.2 V and VN=1.8 V at VDD=5 V (hysteresis ~1.4 V)."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Gate 1 input B. Schmitt-trigger input of the first 2-input NAND gate. NAND output J = NOT(A AND B)."+ },+ {+ "number": "3",+ "name": "J",+ "type": "output",+ "description": "Gate 1 NAND output (J = NOT(A\u00b7B)). CMOS push-pull output, IOH ~ -1.8 mA at VDD=5 V; IOL ~ 3.6 mA at VDD=5 V."+ },+ {+ "number": "4",+ "name": "K",+ "type": "output",+ "description": "Gate 2 NAND output (K = NOT(C\u00b7D)). CMOS push-pull output driven by Schmitt-trigger inputs C and D."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Gate 2 input C. Schmitt-trigger input of the second 2-input NAND gate; pairs with input D to drive output K."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Gate 2 input D. Schmitt-trigger input of the second 2-input NAND gate; pairs with input C to drive output K."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground reference (0 V). Absolute maximum VDD-VSS is 20 V; recommended operating range 3.0 V to 15 V (up to 18 V absolute max)."+ },+ {+ "number": "8",+ "name": "E",+ "type": "input",+ "description": "Gate 3 input E. Schmitt-trigger input of the third 2-input NAND gate; pairs with input F to drive output L."+ },+ {+ "number": "9",+ "name": "F",+ "type": "input",+ "description": "Gate 3 input F. Schmitt-trigger input of the third 2-input NAND gate; pairs with input E to drive output L."+ },+ {+ "number": "10",+ "name": "L",+ "type": "output",+ "description": "Gate 3 NAND output (L = NOT(E\u00b7F)). CMOS push-pull output driven by Schmitt-trigger inputs E and F."+ },+ {+ "number": "11",+ "name": "M",+ "type": "output",+ "description": "Gate 4 NAND output (M = NOT(G\u00b7H)). CMOS push-pull output driven by Schmitt-trigger inputs G and H."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Gate 4 input G. Schmitt-trigger input of the fourth 2-input NAND gate; pairs with input H to drive output M."+ },+ {+ "number": "13",+ "name": "H",+ "type": "input",+ "description": "Gate 4 input H. Schmitt-trigger input of the fourth 2-input NAND gate; pairs with input G to drive output M."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply. Recommended operating range 3.0 V to 15 V; absolute maximum 20 V (spec limit 18 V). Input leakage IIN \u2264 1.2 \u00b5A and quiescent IDD \u2264 1.2 \u00b5A at VDD=18 V, Ta=25 \u00b0C."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2309211039_JSMSEMI-CD4093BM_C5456626.pdf",+ "pages": 5,+ "sha256": "cc5896d280d3cc68",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "JSMSEMI",+ "Package": "SOP-14",+ "Category": "Logic",+ "Pins": "14"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "cd4093bm"+ ],+ "discovery_pitch": "CD4093BM (JSMSEMI) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +174,5 @@ "docs/cd4093bm-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }