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Initial commit: component/cd4093

Ray ·f09e08c5aa ·
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README.mdadded+55
@@ -0,0 +1,55 @@+# CD4093++**GR** · Gates · SOP-14++CD4093 from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Input A of gate 1 (NAND1). Schmitt-trigger input; typical VP=3.2V, VN=1.8V at VDD=5V (hysteresis ~1.4V). Paired with input B to drive output J = NAND(A,B). |+| 2 | B | input | Input B of gate 1 (NAND1). Schmitt-trigger input. Paired with input A to drive output J = NAND(A,B). |+| 3 | J | output | Output of gate 1: J = NAND(A,B). CMOS push-pull output; IOH ~ -1.8 mA @ VDD=5V, IOL ~ 3.6 mA @ VDD=5V. |+| 4 | K | output | Output of gate 2: K = NAND(C,D). CMOS push-pull output. |+| 5 | C | input | Input C of gate 2 (NAND2). Schmitt-trigger input. Paired with D to drive output K. |+| 6 | D | input | Input D of gate 2 (NAND2). Schmitt-trigger input. Paired with C to drive output K. |+| 7 | VSS | power_in | Negative supply / ground reference (0 V). Bypass to VDD locally. |+| 8 | E | input | Input E of gate 3 (NAND3). Schmitt-trigger input. Paired with F to drive output L. |+| 9 | F | input | Input F of gate 3 (NAND3). Schmitt-trigger input. Paired with E to drive output L. |+| 10 | L | output | Output of gate 3: L = NAND(E,F). CMOS push-pull output. |+| 11 | M | output | Output of gate 4: M = NAND(G,H). CMOS push-pull output. |+| 12 | G | input | Input G of gate 4 (NAND4). Schmitt-trigger input. Paired with H to drive output M. |+| 13 | H | input | Input H of gate 4 (NAND4). Schmitt-trigger input. Paired with G to drive output M. |+| 14 | VDD | power_in | Positive supply. Recommended operating range 3-15 V (absolute max 20 V). Bypass to VSS locally with a 0.1 uF ceramic. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GR |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `CD4093S`+- `CD4093D`++## CAD (KiCad official)++- Symbol: `CD4093`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GR datasheet](docs/cd4093-datasheet.pdf) (5 pp, sha256 `cce1d51c3b338507`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4093-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "cd4093",+  "version": "0.1.0",+  "type": "component",+  "description": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "cd4093"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4093.kicad_sym",+    "cd4093.kicad_mod",+    "cd4093.glb",+    "cd4093.step",+    "cd4093.lbr",+    "docs/hero.png",+    "docs/cd4093-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file