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cd4093: factory component page (tier=lcsc)

Ray ·7cb335de1d · ·parent a2278f0
1 file changed +152−8
page.json+152−8
@@ -1,13 +1,162 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4093",+  "title": "CD4093",+  "brief": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "cd4093"   ],+  "component": {+    "mpn": "CD4093",+    "manufacturer": "GR",+    "package": "SOP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Gates",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403121624_GR-CD4093_C22357620.pdf",+    "parts": {+      "symbol": "cd4093.kicad_sym",+      "footprint": "cd4093.kicad_mod",+      "model_3d": "cd4093.glb",+      "model_3d_step": "cd4093.step",+      "lbr": "cd4093.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Input A of gate 1 (NAND1). Schmitt-trigger input; typical VP=3.2V, VN=1.8V at VDD=5V (hysteresis ~1.4V). Paired with input B to drive output J = NAND(A,B)."+      },+      {+        "number": "2",+        "name": "B",+        "type": "input",+        "description": "Input B of gate 1 (NAND1). Schmitt-trigger input. Paired with input A to drive output J = NAND(A,B)."+      },+      {+        "number": "3",+        "name": "J",+        "type": "output",+        "description": "Output of gate 1: J = NAND(A,B). CMOS push-pull output; IOH ~ -1.8 mA @ VDD=5V, IOL ~ 3.6 mA @ VDD=5V."+      },+      {+        "number": "4",+        "name": "K",+        "type": "output",+        "description": "Output of gate 2: K = NAND(C,D). CMOS push-pull output."+      },+      {+        "number": "5",+        "name": "C",+        "type": "input",+        "description": "Input C of gate 2 (NAND2). Schmitt-trigger input. Paired with D to drive output K."+      },+      {+        "number": "6",+        "name": "D",+        "type": "input",+        "description": "Input D of gate 2 (NAND2). Schmitt-trigger input. Paired with C to drive output K."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference (0 V). Bypass to VDD locally."+      },+      {+        "number": "8",+        "name": "E",+        "type": "input",+        "description": "Input E of gate 3 (NAND3). Schmitt-trigger input. Paired with F to drive output L."+      },+      {+        "number": "9",+        "name": "F",+        "type": "input",+        "description": "Input F of gate 3 (NAND3). Schmitt-trigger input. Paired with E to drive output L."+      },+      {+        "number": "10",+        "name": "L",+        "type": "output",+        "description": "Output of gate 3: L = NAND(E,F). CMOS push-pull output."+      },+      {+        "number": "11",+        "name": "M",+        "type": "output",+        "description": "Output of gate 4: M = NAND(G,H). CMOS push-pull output."+      },+      {+        "number": "12",+        "name": "G",+        "type": "input",+        "description": "Input G of gate 4 (NAND4). Schmitt-trigger input. Paired with H to drive output M."+      },+      {+        "number": "13",+        "name": "H",+        "type": "input",+        "description": "Input H of gate 4 (NAND4). Schmitt-trigger input. Paired with G to drive output M."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply. Recommended operating range 3-15 V (absolute max 20 V). Bypass to VSS locally with a 0.1 uF ceramic."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403121624_GR-CD4093_C22357620.pdf",+        "pages": 5,+        "sha256": "cce1d51c3b338507",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "GR",+      "Package": "SOP-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd4093"+  ],+  "discovery_pitch": "CD4093 (GR) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +174,5 @@     "docs/cd4093-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file