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Set visibility: public

Ray ·6d23d40d2a ·1mo ago ·parent d9b04b0
1 file changed +8−5
page.json+8−5
@@ -44,13 +44,13 @@         "number": "3",         "name": "E1",         "type": "output",-        "description": "Output of AOI gate 1. Realizes E1 = INH1 + A1\u00b7B1 + C1\u00b7D1 (a 3-input NOR of INHIBIT1 with the two AND products A1\u00b7B1 and C1\u00b7D1). Standardized symmetrical CMOS output."+        "description": "Output of AOI gate 1. Realizes E1 = INH1 + A1·B1 + C1·D1 (a 3-input NOR of INHIBIT1 with the two AND products A1·B1 and C1·D1). Standardized symmetrical CMOS output."       },       {         "number": "4",         "name": "E2",         "type": "output",-        "description": "Output of AOI gate 2. Realizes E2 = INH2 + A2\u00b7B2 + C2\u00b7D2 (3-input NOR of INHIBIT2 with the two AND products A2\u00b7B2 and C2\u00b7D2). Standardized symmetrical CMOS output."+        "description": "Output of AOI gate 2. Realizes E2 = INH2 + A2·B2 + C2·D2 (3-input NOR of INHIBIT2 with the two AND products A2·B2 and C2·D2). Standardized symmetrical CMOS output."       },       {         "number": "5",@@ -86,13 +86,13 @@         "number": "10",         "name": "INHIBIT1",         "type": "input",-        "description": "Inhibit control for AOI gate 1. When high, forces E1 low regardless of the A1/B1/C1/D1 inputs (INH1 appears in the NOR term of E1 = INH1 + A1\u00b7B1 + C1\u00b7D1). CMOS logic input."+        "description": "Inhibit control for AOI gate 1. When high, forces E1 low regardless of the A1/B1/C1/D1 inputs (INH1 appears in the NOR term of E1 = INH1 + A1·B1 + C1·D1). CMOS logic input."       },       {         "number": "11",         "name": "INHIBIT2",         "type": "input",-        "description": "Inhibit control for AOI gate 2. When high, forces E2 low regardless of the A2/B2/C2/D2 inputs (INH2 appears in the NOR term of E2 = INH2 + A2\u00b7B2 + C2\u00b7D2). CMOS logic input."+        "description": "Inhibit control for AOI gate 2. When high, forces E2 low regardless of the A2/B2/C2/D2 inputs (INH2 appears in the NOR term of E2 = INH2 + A2·B2 + C2·D2). CMOS logic input."       },       {         "number": "12",@@ -212,5 +212,8 @@     "docs/cd4085bm-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file