CD4085BM

@@ -0,0 +1,63 @@+# CD4085BM++**Texas Instruments** · Logic Gates · SOIC-14++CD4085BM from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A1 | input | Data input A of the first AND gate in AOI gate 1. Combined with B1 into the first 2-input AND of AOI 1. CMOS logic input (VIL max 1.5/3/4 V and VIH min 3.5/7/11 V at VDD = 5/10/15 V). |+| 2 | B1 | input | Data input B of the first AND gate in AOI gate 1. Combined with A1 into the first 2-input AND of AOI 1. CMOS logic input. |+| 3 | E1 | output | Output of AOI gate 1. Realizes E1 = INH1 + A1·B1 + C1·D1 (a 3-input NOR of INHIBIT1 with the two AND products A1·B1 and C1·D1). Standardized symmetrical CMOS output. |+| 4 | E2 | output | Output of AOI gate 2. Realizes E2 = INH2 + A2·B2 + C2·D2 (3-input NOR of INHIBIT2 with the two AND products A2·B2 and C2·D2). Standardized symmetrical CMOS output. |+| 5 | A2 | input | Data input A of the first AND gate in AOI gate 2. Combined with B2 into the first 2-input AND of AOI 2. CMOS logic input. |+| 6 | B2 | input | Data input B of the first AND gate in AOI gate 2. Combined with A2 into the first 2-input AND of AOI 2. CMOS logic input. |+| 7 | VSS | power_in | Negative supply / ground reference for the device. Absolute maximum input voltage referenced to VSS is -0.5 V to VDD+0.5 V. |+| 8 | C2 | input | Data input C of the second AND gate in AOI gate 2. Combined with D2 into the second 2-input AND of AOI 2. CMOS logic input. |+| 9 | D2 | input | Data input D of the second AND gate in AOI gate 2. Combined with C2 into the second 2-input AND of AOI 2. CMOS logic input. |+| 10 | INHIBIT1 | input | Inhibit control for AOI gate 1. When high, forces E1 low regardless of the A1/B1/C1/D1 inputs (INH1 appears in the NOR term of E1 = INH1 + A1·B1 + C1·D1). CMOS logic input. |+| 11 | INHIBIT2 | input | Inhibit control for AOI gate 2. When high, forces E2 low regardless of the A2/B2/C2/D2 inputs (INH2 appears in the NOR term of E2 = INH2 + A2·B2 + C2·D2). CMOS logic input. |+| 12 | C1 | input | Data input C of the second AND gate in AOI gate 1. Combined with D1 into the second 2-input AND of AOI 1. CMOS logic input. |+| 13 | D1 | input | Data input D of the second AND gate in AOI gate 1. Combined with C1 into the second 2-input AND of AOI 1. CMOS logic input. |+| 14 | VDD | power_in | Positive supply. Recommended supply-voltage range 3 V to 18 V; absolute maximum -0.5 V to 20 V. Parametric ratings characterized at 5 V, 10 V, and 15 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++Same part, different packaging or reel option.++- `CD4085BMM`+- `CD4085BMMT`+- `CD4085BMM96`+- `CD4085BMNSR`+- `CD4085BME`+- `CD4085BMF`+- `CD4085BMF3A`+- `CD4085BMPW`+- `CD4085BMPWR`++## CAD (KiCad official)++- Symbol: `CD4085BM`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4085b) (None pp, sha256 `0169c8587f0ccebf`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4085bm-datasheet.pdf)

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