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Initial commit: component/cd4082be

Ray ·2d6d343dd7 ·2d ago
2 files changed +246
README.mdadded+50
@@ -0,0 +1,50 @@+# CD4082BE++**Texas Instruments** · Logic Gates · DIP-14++CD4082BE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | J | output | Gate 1 output, J = A·B·C·D (4-input AND). |+| 2 | D | input | Gate 1 input D. |+| 3 | C | input | Gate 1 input C. |+| 4 | B | input | Gate 1 input B. |+| 5 | A | input | Gate 1 input A. |+| 6 | NC | unconnected | No connection. |+| 7 | VSS | power_in | Negative supply / ground (VSS). |+| 8 | NC | unconnected | No connection. |+| 9 | E | input | Gate 2 input E. |+| 10 | F | input | Gate 2 input F. |+| 11 | G | input | Gate 2 input G. |+| 12 | H | input | Gate 2 input H. |+| 13 | K | output | Gate 2 output, K = E·F·G·H (4-input AND). |+| 14 | VDD | power_in | Positive supply voltage (VDD). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | DIP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD4082BE`+- Footprint: `Package_DIP:DIP-14_W7.62mm`+- 3D model: DIP-14 (KiCad packages3D, STEP)+- 3D model files: `cd4082be-etched.step` / `cd4082be-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4082be.step` / `cd4082be.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4082b) (34 pp, sha256 `68c6167d1ae45286`, retrieved 2026-10-03, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4082be-datasheet.pdf)
page.jsonadded+196
@@ -0,0 +1,196 @@+{+  "slug": "cd4082be",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "cd4082be",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4082be.kicad_sym",+    "cd4082be.kicad_mod",+    "cd4082be.glb",+    "cd4082be.step",+    "cd4082be.lbr",+    "docs/hero.png",+    "docs/cd4082be-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "cd4082be-hero.glb",+    "cd4082be-hero.overlay.json"+  ],+  "component": {+    "mpn": "CD4082BE",+    "manufacturer": "Texas Instruments",+    "package": "DIP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gates",+    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4082b",+    "parts": {+      "symbol": "cd4082be.kicad_sym",+      "footprint": "cd4082be.kicad_mod",+      "model_3d": "cd4082be-hero.glb",+      "model_3d_plain": "cd4082be.glb",+      "model_3d_step": "cd4082be-etched.step",+      "model_3d_step_plain": "cd4082be.step",+      "lbr": "cd4082be.lbr"+    },+    "distributor_links": {+      "lcsc": 5228,+      "digikey": "2156-CD4082BE-ND",+      "mouser": "595-CD4082BE"+    },+    "distributor_check": {+      "checked_at": "2026-10-03T04:46:46Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "2156-CD4082BE-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-CD4082BE",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "J",+        "type": "output",+        "description": "Gate 1 output, J = A·B·C·D (4-input AND)."+      },+      {+        "number": "2",+        "name": "D",+        "type": "input",+        "description": "Gate 1 input D."+      },+      {+        "number": "3",+        "name": "C",+        "type": "input",+        "description": "Gate 1 input C."+      },+      {+        "number": "4",+        "name": "B",+        "type": "input",+        "description": "Gate 1 input B."+      },+      {+        "number": "5",+        "name": "A",+        "type": "input",+        "description": "Gate 1 input A."+      },+      {+        "number": "6",+        "name": "NC",+        "type": "unconnected",+        "description": "No connection."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground (VSS)."+      },+      {+        "number": "8",+        "name": "NC",+        "type": "unconnected",+        "description": "No connection."+      },+      {+        "number": "9",+        "name": "E",+        "type": "input",+        "description": "Gate 2 input E."+      },+      {+        "number": "10",+        "name": "F",+        "type": "input",+        "description": "Gate 2 input F."+      },+      {+        "number": "11",+        "name": "G",+        "type": "input",+        "description": "Gate 2 input G."+      },+      {+        "number": "12",+        "name": "H",+        "type": "input",+        "description": "Gate 2 input H."+      },+      {+        "number": "13",+        "name": "K",+        "type": "output",+        "description": "Gate 2 output, K = E·F·G·H (4-input AND)."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply voltage (VDD)."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-sonnet-5-5",+        "primary_mode": "text+vision",+        "consensus_model": "claude-opus-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: Pinout read from the page-4 terminal assignment image (TOP VIEW, CD4082B). The CD4082BE is sold in t",+          "vision extraction: provenance cannot be text-verified; needs consensus"+        ],+        "pages_sent": 34,+        "cost_usd": 0.6658,+        "at": "2026-10-03T04:46:25"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/cd4082b",+        "pages": 34,+        "sha256": "68c6167d1ae45286",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file